Y TEORÍA DE RESTRICCIONES
5.3 COMPARACIÓN ENTRE LOS ENFOQUES DE CONTABILIDAD TRADICIONAL Y TEORÍA DE RESTRICCIONES
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22 Assura Decks
NOTE: This PDK revision B04_PB does not incorporate Assura Decks. The following descriptions are for reference only
The user needs to do the following in order to implement and use the Assura Verification decks:
1) Create a directory named:
• assura_umc18mmrf_tech
2) Place all Assura decks in the directory created above ( assura_umc18mmrf_tech).
3) Create a file named:
• assura_tech.lib
4) In this file ( assura_tech.lib ), the user needs to enter only one line:
DEFINE umc18mmrf_rcx ./assura_umc18mmrf_tech
Once these four steps have been completed, the user will then be able to run Assura Verification on this PDK.
The user needs the licenses for these tools to perform verification. When performing verification you have to provide the library name to the verification deck. Select the desired switches before starting the verification run. Refrain from working on the target layout being verified while the run is in progress.
Following are the tar files for the description of Assura verification setup only:
Assura RCX tar file name:
G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC-ASSURA-LPE-1.1-P3 Files Included:
Topm_20k.tar Files Included:
g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul
UM180FDKMFC000000A_B g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rsf
umc_ant_assura_all.0.rul umc_ant_assura_all-.0.rsf
Version: DRC version: 2.2-p5 ANT version: 0
Date: DRC date: 04/11/03
ANT date: 04/21/03
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22.1 Assura DRC
The following 3 Assura DRC files were tested with the PDK and were placed in the assura_umc18mmrf_tech directory:
•
g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p 5.rul.
• umc_ant_assura_all.0.rul
• assuraESD.rul
The following switches are available in the
g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul:
Technology Switches:
• BDSP_rule – checks rules for the bordered SP SRAM core regions
• BLSP1_rule – checks the rules for the borderless SP SRAM core regions
• BLSP_rule – checks the rules for the Virage SP SRAM core regions
• DP1_rule – checks the rules for the DP1 SRAM core regions
• DP2_rule – checks the rules for the DP2 SRAM core regions
• DP_rule – checks the rules for the DP SRAM core regions
• ROM_rule – checks the rules for the ROM regions
• metal2_is_top – specifies 2-Metal Technology
• metal3_is_top – specifies 3-Metal Technology
• metal4_is_top – specifies 4-Metal Technology
• metal5_is_top – specifies 5-Metal Technology
• top_metal_is_thick – specifies Thick Top Metal Chip-Level Switches:
• SR – Seal ring rules are checked Run-Time Intensive Switches:
• check_max_metal_space – Maximum Metal spacing rules are
checked
• check_density – Metal coverage rules are checked
• check_slots – Slot rules are checked
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By default, if none of the switches are set, the file will assume the following:
• The design incorporates 6-metal technology
• Off-grid checks will be performed
• The chip-level checks will NOT be performed
• The run-time intensive checks will NOT be performed.
22.2 Assura Antenna
The following Assura Antenna file was tested with the PDK and was placed in the assura_umc18mmrf_tech directory:
• umc_ant_assura_all.0.rul
The following switches are available in the assuraANT.rul file:
Technology Switches:
• metal1_is_top – specifies 1-Metal Technology
• metal2_is_top – specifies 2-Metal Technology • metal3_is_top – specifies 3-Metal Technology • metal4_is_top – specifies 4-Metal Technology • metal5_is_top – specifies 5-Metal Technology
• metal6_is_top – specifies 6-Metal Technology
By default, if none of the switches are set, the file will assume 6-metal process.
Antenna Check Format Switches:
• Check_All_Top_Antenna – Performs one level area and perimeter antenna checks. For example, checks m3 area/gate area and m3 perimeter/gate perimeter check.
• Check_Cumulative_Area_Antenna – Performs cumulative area antenna checks.
• Check_Cumulative_Perimeter_Antenna – Performs cumulative perimeter antenna checks.
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22.3 Assura ESD
The Assura Antenna files tested with the PDK were placed in the assura_umc18mmrf_tech directory and are named:
• assuraESD.rul
No switches are available in the assuraESD.rul file.
ASSURA DRC FORM
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22.4 Assura LVS
The Assura LVS files tested with the PDK were placed in the assura_umc18mmrf_tech directory:
Please see usage notes in extract.rul for more information.
The following switches are available in the extract.rul file:
• Artisan_Lib – for extraction of devices from Artisan libraries
• Skip_Soft-Connect_Checks - Select the switch to skip the reporting of multStamp, floating, and multConnect errors.
By default, this switch is not set.
• Top_Metal_Thickness--20K – Sets Metal Resistor Coefficients for 20KA thick Top Metal.
To avoid RCX run-time errors, use the switches below to skip the extraction statements of the devices without IVPCELL view.
• Skip_Logic_Device_Extraction—Skips extraction of logic devices.
• Skip_Mixed_Mode_Device_Extraction—Skips extraction of Mixed Mode ( _MM) devices.
• Skip_RF_Device_Extraction—Skips extraction of RF ( _RF) devices.
DO NOT SELECT ANY OF THE FOLLOWING SWITCHES:
• Top_Metal—ME4 – This is not supported in this PDK.
• Top_Metal—ME5 – This is not supported in this PDK.
UM180FDKMFC000000A_B The default switch is for the 8KA 1P6M process.
ASSURA LVS FORM
22.5 Assura RCX
The Assura RCX files tested with the PDK were placed in the following directory:
• assura_umc18mmrf_tech - Directory where Assura RCX files are provided
UM180FDKMFC000000A_B Please consult the Assura RCX users manual for available RCX options.
NOTE: The av_extracted view is not supported in these Assura rules.
To enable av_extracted views please follow the instructions below:
1) Convert the extract rules with the “Skip_Logic_Device_Extraction” switch set for capgen input
The following files should be found in your assura_umc18mmrf_tech directory:
umc18mm_20k_rcx.rsf - sample RSF to run Assura RCX
Additional files - RCXdspfINIT, RCXspiceINIT, RCXutilities - cap.so, s2d.log, caps2d
- paxfile_coeff, rcxfs.dat
The capgen lvsfile is created from the Assura extract rules file. A sample RSF file, lvsfile.rsf is shown below to do this.
The Cadence PDK compatible Assura extract rules file, extract.rul is included. You may use this or your own file. Change the
lvsfile.rsf file as needed. Within the assura_umc18mmrf_tech directory, run Assura from Unix:
Sample lvsfile.rsf:
/**********************************************************************
UM180FDKMFC000000A_B
Assura RCX sample RSF for capgen lvsfile creation
Use this file to create the capgen "lvsfile" from extract.rul
***********************************************************************/
avParameters(
?rulesFile "extract.rul"
?rcxFile "lvsfile"
?inputLayout ("df2" "dummyLayoutName" ) ?cellName "dummyCellname"
?viewName “dummyviewName”
?cdslib “./cds.lib”
?set “Skip_Logic_Device_Extraction”
?runName "lvs_convert"
?compileOnly t )
Note: Set ?inputLayout, ?cellName and ?viewName to point to data.
2) Run “assura lvsfile.rsf > lvs_convert.log” from the Unix prompt
The output will be the file "lvsfile" which will be used as an input to capgen. The other files from the run (lvs_convert.???) can be deleted.
3) Execute the second capgen command from Unix prompt within the assura_umc18mmrf_tech.
% capgen -C -lvs lvsfile -p2lvs p2lvsfile -mos_diff_ap -cap_unit 1 .
Note: The period “.” at the end of the command stands for current directory.
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ASSURA RCX FORM
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23 DEVICE SPECIFICATIONS
Model and Layout Source
Device Description
Spectre
N_BPW_18_MM 1.8 volt triple-well NMOS transistor y y y Pcell
N_33_MM 3.3 volt NMOS transistor y y y Pcell
N_BPW_33_MM 3.3 volt triple-well NMOS transistor y y y Pcell
N_LV_18_MM 1.8 volt low vt NMOS transistor y y y Pcell
N_L18W500_18_RF 1.8 volt variable finger RF NMOS transistor y y y Pcell N_L34W500_33_RF 3.3 volt variable finger RF NMOS transistor y y y Pcell N_PO7W500_18_RF 1.8 volt variable length RF NMOS transistor y y y Pcell N_PO7W500_33_RF 3.3 volt variable length RF NMOS transistor y y y Pcell P_L18W500_18_RF 1.8 volt variable finger RF PMOS transistor y y y Pcell P_L34W500_33_RF 3.3 volt variable finger RF PMOS transistor y y y Pcell P_PO7W500_18_RF 1.8 volt variable length RF PMOS transistor y y y Pcell P_PO7W500_33_RF 3.3 volt variable length RF PMOS transistor y y y Pcell
Resistor
RSND_MM N+ diffused resistor w/ salicide y y y Pcell
RSPD_MM P+ diffused resistor w/ salicide y y y Pcell
RNPPO_MM P+ poly resistor w/o salicide y y y Pcell
MIMCAPS_MM Single-squared MM Metal capacitor y y y Pcell
NCAP_MM NMOS gate capacitor y y y Pcell
PNP_V100X100_MM Vertical substrate PNP ( 10x10 ) y y y Fixed
Inductor
L_SLCR20K_RF Circular spiral RF inductor y y y Pcell
Bond Pad
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Varactor
VARDIOP_RF P+/Nwell RF diode varactor y y y Pcell
VARMIS_18_RF 1.8V N+/Nwell RF MIS varactor y y y Pcell
23.1 MOS FORMAL PARAMETERS
l (gate length in microns)
Device min Value Got from Design Rule # max Value Got from
N_18_MM 180n Design Rules 4.14Aa 50u Spectre model N_BPW_18_MM 180n Design Rules 4.14Aa 50u Spectre model N_33_MM 340n Design Rules 4.14Ab 50u Spectre model N_BPW_33_MM 340n Design Rules 4.14Ab 50u Spectre model N_LV_18_MM 240n Design Rules 4.7Aa 50u Spectre model N_LV_33_MM 500n Design Rules 4.9A 50u Spectre model N_ZERO_18_MM 300n Design Rules 4.8A 50u Spectre model N_ZERO_33_MM 500n Design Rules 4.7Ab 50u Spectre model
P_18_MM 180n Design Rules 4.14Ba 50u Spectre model P_33_MM 340n Design Rules 4.14Bb 50u Spectre model P_LV_18_MM 240n Design Rules 4.4A 50u Spectre model P_LV_33_MM 500n Design Rules 4.5A 50u Spectre model
N_18_MM 240n Spectre model 100u Spectre model N_BPW_18_MM 240n Spectre model 100u Spectre model N_33_MM 240n Spectre model 100u Spectre model N_BPW_33_MM 240n Spectre model 100u Spectre model N_LV_18_MM 240n Spectre model 100u Spectre model N_LV_33_MM 800n Spectre model 100u Spectre model N_ZERO_18_MM 240n Spectre model 100u Spectre model N_ZERO_33_MM 800n Spectre model 100u Spectre model
P_18_MM 240n Spectre model 100u Spectre model P_33_MM 240n Spectre model 100u Spectre model P_LV_18_MM 240n Spectre model 100u Spectre model P_LV_33_MM 800n Spectre model 100u Spectre model
Device min Value Got from max Value Got from
N_18_MM 1 Default 100 PDK standard N_BPW_18_MM 1 Default 100 PDK standard N_33_MM 1 Default 100 PDK standard N_BPW_33_MM 1 Default 100 PDK standard N_LV_18_MM 1 Default 100 PDK standard N_LV_33_MM 1 Default 100 PDK standard N_ZERO_18_MM 1 Default 100 PDK standard N_ZERO_33_MM 1 Default 100 PDK standard
P_18_MM 1 Default 100 PDK standard P_33_MM 1 Default 100 PDK standard P_LV_18_MM 1 Default 100 PDK standard P_LV_33_MM 1 Default 100 PDK standard
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23.2 RF MOS FORMAL PARAMETERS
Device Name
N_L18W500_18_RF 180.0n Spectre model 180.0n Spectre model N_L34W500_33_RF 340.0n Spectre model 340.0n Spectre model N_PO7W500_18_RF 200n Spectre model 500n Spectre model N_PO7W500_33_RF 340.0n Spectre model 800n Spectre model P_L18W500_18_RF 180.0n Spectre model 180.0n Spectre model P_L34W500_33_RF 340.0n Spectre model 340.0n Spectre model P_PO7W500_18_RF 200n Spectre model 500n Spectre model P_PO7W500_33_RF 340.0n Spectre model 800n Spectre model
Device Name
N_L18W500_18_RF 5u Spectre model 5u Spectre model N_L34W500_33_RF 5u Spectre model 5u Spectre model N_PO7W500_18_RF 5u Spectre model 5u Spectre model N_PO7W500_33_RF 5u Spectre model 5u Spectre model P_L18W500_18_RF 5u Spectre model 5u Spectre model P_L34W500_33_RF 5u Spectre model 5u Spectre model P_PO7W500_18_RF 5u Spectre model 5u Spectre model P_PO7W500_33_RF 5u Spectre model 5u Spectre model
Device Name
N_L18W500_18_RF 5 Spectre model 21 Spectre model N_L34W500_33_RF 5 Spectre model 21 Spectre model N_PO7W500_18_RF 7 Spectre model 7 Spectre model N_PO7W500_33_RF 7 Spectre model 7 Spectre model P_L18W500_18_RF 5 Spectre model 21 Spectre model P_L34W500_33_RF 5 Spectre model 21 Spectre model P_PO7W500_18_RF 7 Spectre model 7 Spectre model P_PO7W500_33_RF 7 Spectre model 7 Spectre model
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23.3 RESISTOR FORMAL PARAMETERS
r (resistance in Ohms)
Device min Value Got from Design Rule # max Value Got from Design Rule #
RSND_MM 168.000m Calculation Calc.1 33.3107K Calculation Calc. 3 RSPD_MM 168.000m Calculation Calc.1 33.3107K Calculation Calc. 3 RNPPO_MM 21.1085 Calculation Calc.1 2.62455M Calculation Calc. 3 RNNPO_MM 5.11481 Calculation Calc.1 1.35984M Calculation Calc. 3 RSNWELL_MM 31.376 Calculation Calc.1 6.19403K Calculation Calc. 3 RNHR1000_MM 43.263 Calculation Calc.5 7.56992M Calculation Calc. 6 RNND_MM 2.39596 Calculation Calc.1 291.817K Calculation Calc. 3 RNPD_MM 4.73918 Calculation Calc.1 484.5K Calculation Calc. 3 RM1_MM 2.82975m Calculation Calc.2 6.41667 Calculation Calc.4 RM1_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM3_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM4_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM5_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM6_MM 2.16275m Calculation Calc.2 1.86364 Calculation Calc.4
w (width In microns)
Device min Value Got from Design Rule # max Value Got from
RSND_MM 240n Design Rules 4.1Aa 20u PDK Standard RSPD_MM 240n Design Rules 4.1Ab 20u PDK Standard RNPPO_MM 180n Design Rules 4.14Aa 20u PDK Standard RNNPO_MM 180n Design Rules 4.14Ba 20u PDK Standard RSNWELL_MM 1.5u Design Rules 4.2Ab 20u PDK Standard RNHR1000_MM 180n Design Rules 4.14Aa 20u PDK Standard RNND_MM 240n Design Rules 4.1Aa 20u PDK Standard
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Note:
Calc.1 ( Salicided sheet resistance ) * ( minL + deltaL ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW )
Calc.2 ( Salicided sheet resistance ) * ( minL ) / ( maxW )
Calc.3 ( Salicided sheet resistance ) * ( maxL + deltaL ) / ( minW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( minW + deltaW)
Calc.4 ( Salicided sheet resistance ) * ( maxL ) / ( minW )
Calc.5 ( Salicided sheet resistance ) * ( minL -0.4um ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW )
Calc.6 ( Salicided sheet resistance ) * ( maxL -0.4um ) / ( minW + deltaW ) + 2 * ( non-salicided sheet resistance ) / ( minW + deltaW )
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23.4 RF RESISTOR FORMAL PARAMETERS
Device Name
RNHR_RF 972.1002 Calculation 10.52856K Calculation RNNPO_RF 136.6264 Calculation 1.205465K Calculation RNPPO_RF 467.7584 Calculation 3.710338K Calculation
Device Name
RNHR_RF 2u Spectre model 10u Spectre model RNNPO_RF 2u Spectre model 10u Spectre model RNPPO_RF 2u Spectre model 10u Spectre model
Device Name
RNHR_RF 2u Spectre model 100u Spectre model RNNPO_RF 2u Spectre model 100u Spectre model RNPPO_RF 2u Spectre model 100u Spectre model
NCAP_MM 1.8618f Design Rules Dim.1 3.3011p Design Rules Dim.2 PCAP_MM 1.8618f Design Rules Dim.1 3.3011p Design Rules Dim.2
l (length in Metres)
Device min Value Got from Design Rule # max Value Got from
MIMCAPS_MM 1.84u Design Rules Dim.3 100u Spectre model NCAP_MM 180n Design Rules 4.14Aa 20u Spectre model PCAP_MM 180n Design Rules 4.14Ba 20u Spectre model
W (width in Metres)
Device min Value Got from max Value Got from
MIMCAPS_MM 1.84u Dim.3 100u Spectre model
NCAP_MM 440n Dim.4 20u Spectre model
PCAP_MM 440n Dim.5 20u Spectre model
Fingers (number of Fingers) Device min Value Got from max Value Got from
MIMCAPS_MM
NCAP_MM 1 Default 50 PDK Standard
PCAP_MM 1 Default 50 PDK Standard
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Note:
Dim.1 minW * minL * ( Area Capacitance ) + 2 * ( minW + minL ) * ( Fringe Capacitance )
Dim.2 maxW * maxL * ( Area Capacitance ) + 2 * ( maxW + maxL ) * ( Fringe Capacitance )
Dim.3 ( minWidth of VI5 ) + 2 * ( MMC enclosure of VI5 )
4.30A 4.29D
Dim.4 ( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact )
4.19A 4.19G
Dim.5 ( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact )
4.19A 4.19F
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23.6 RF CAPACITOR FORMAL PARAMETERS
MIMCAPM_RF 103.00f Calculation 5.047p Calculation
Device Name
MIMCAPM_RF 10u Spectre model 70u Spectre model
Device Name
MIMCAPM_RF 10u Spectre model 70u Spectre model
Device Name
nx (Multi Square
X)
min Value Got from max Value Got from
MIMCAPM_RF 1 Spectre model 7 Spectre model
Device Name
ny (Multi Square
Y)
min Value Got from max Value Got from
MIMCAPM_RF 1 Spectre model 7 Spectre model
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23.7 INDUCTOR FORMAL PARAMETERS
Device Name
L_SLCR20K_RF 567.9646p Calculation 14.27438n Calculation
Device Name
L_SLCR20K_RF 126u Spectre model 238u Spectre model
Device Name
w (Width)
min Value Got from max Value Got from
L_SLCR20K_RF 6u Spectre model 20u Spectre model
Device Name
L_SLCR20K_RF 1.5 Spectre model 5.5 Spectre model
23.8 BOND PAD FORMAL PARAMETERS
Device Name
index
min Value Got from max Value Got from
PAD_RF 1 Spectre model 5 Spectre model
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23.9 VARACTOR FORMAL PARAMETERS
Device Name
VARDIOP_RF 406.32f Calculation 1.62528p Calculation
VARMIS_18_RF N/A N/A
VARMIS_18_RF 1.030819p Calculation 5.154096p Calculation
Device Name
VARDIOP_RF 30 Spectre model 120 Spectre model
VARMIS_18_RF 24 Spectre model 120 Spectre model
23.10 BIPOLAR FORMAL PARAMETERS
The bipolar devices have fixed layouts and do not have any formal editable parameters.
23.11 DIODES FORMAL PARAMETERS
The diode devices have fixed layouts and do not have any formal editable parameters.
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