Against the backdrop of the recognition of SOI CMOS as a key technology for logic LSI of higher performance and lower power consumption, the fact that SOI substrates based on Si substrates have higher quality and lower cost are extremely important. A thin-film SOI substrate that has a surface layer of Si that is less than 100 nm thick serves as the substrate for forming the fine CMOS devices of a logic LSI chip. In addition, various factors of substrate quality, including the quality of the SOI layer, which affects the reliability of the gate oxide layer and the standby leak current, the uniformity of thickness of the SOI layer and the BOX layer and controllability in the production process, roughness of the SOI surface, the characteristics of the boundary between the BOX layer and the SOI layer, whether or not there are pinholes in the BOX layer, and the breakdown voltage, must be cleared [8,9]. Furthermore, for the production of SOI CMOS with the same production line, as is used for CMOS on bulk Si substrate, the absence of metal contamination and a metal contamination gettering capability are needed.
Selective CVD−W SOI (50 nm) BOX (120 nm) ML1 ML2 ML3 ML4 1 mm
FIGURE 2.82 Cross section TEM image of fully depleted SOI CMOS.
Performance: SOI vs. bulk 48-bit MPLs 0.25 µm gate 1.0 1.2 1.4 1.6 1.8 2.0 0 20 40 60 80 Supply voltage (V) Multiplication time (ns) Bulk SOI 46% 40% 32%
FIGURE 2.83 Comparison of a 48 b multiplier performance between SOI and bulk Si using 250 nm CMOS technology.
Also, adaptability for mass production, cost reduction, and larger wafer diameters must be considered. From this point of view, remarkable progress has been achieved in thin-film SOI substrates for fine CMOS over these past several years. In particular, the SOI substrates that have attracted attention are broadly classified into SIMOX (separation by implanted oxygen) substrates and wafer bonding (WB) substrates, as shown in Fig. 2.84. A SIMOX substrate is formed by oxygen ion implantation and high-temperature annealing. Wafer bonding substrates, on the other hand, are made by bonding together a Si substrate on which an oxide layer is formed, which is called a device wafer (DW) because the devices are formed on it, and another substrate, called the handle wafer (HW), and then thinning down the DW from the surface so as to create an SOI layer of the desired thickness. For fine CMOS, a thin SOI layer of less than 100 nm must be fabricated to a layer thickness accuracy of within±5%–10%. Because that accuracy is difficult to achieve with simple grinding or polishing technology, various methods are being studied. Of those, two methods that are attracting attention are ELTRAN (epitaxial layer transfer) [10] and UNIBOND [11]. ELTRAN involves the use of a porous Si layer formed by anodizing and a Si epitaxial layer to form the separation layer of the DW and HW; the UNIBOND substrate uses hydrogen ion implantation in the formation of the peel-off layer. It has already been demonstrated that the application of these SOI substrates to 300 mm wafers and mass production is technologically feasible, and because this is also considered to be important from the viewpoint of application to logic LSI chips, which are a typical representative of MPUs, an overview of the technology and issues is presented in the next section.
2.4.3.1 SIMOX Substrates
For SIMOX substrates, the BOX layer is formed by the implantation of a large quantity of oxygen ions at energies of about 200 keV followed by annealing at high temperatures above 13008C, as shown in Fig. 2.85 [4]. Because the amount of oxygen implanted and the implantation energy are controlled electronically with high accuracy, there is excellent control of the uniformity of the thickness of the SOI layer and the BOX layer. A substrate obtained by high-dose oxygen implantation in the order of 1018cm2
SIMOX Separation by implanted oxygen ELTRAN Epitaxial layer transfer Low-dose High-dose UNIBOND WB Wafer bonding BESOI Bond and etch-back SOI ITOX-SIMOX Internal thermal oxidation
FIGURE 2.84 SOI material technologies for production.
ITOX-SIMOX
Thermal oxide Thermal oxide
SOI (320nm) SOI (62 nm)
BOX (80nm) BOX (120nm)
O+ ions
O+ Ions implantation
Si substrate Si substrate Si substrate
High-temperature
annealing >1300⬚C
Internal thermal
oxidation >1300⬚C
FIGURE 2.85 Main process steps of ITOX-SIMOX.
is called a high-dose SIMOX substrate and has a BOX layer thickness of about 400–500 nm. The presence of 108cm2or more dislocation density in the SOI layer and the long period required for the high-dose oxygen ion implantation create problems with respect to the quality of the SOI layer and the cost and mass productivity of the substrate. On the other hand, it has been discovered that if the oxygen ion implantation dose is lowered to about 431017cm2, there are dose regions in which the dislocation density is reduced to below 300 cm2, resulting in high quality of the SOI layer and lower substrate cost [12]. Such a substrate is referred to as a low-dose SIMOX substrate. However, the BOX layer of this substrate is thin (about 90 nm), making it necessary to reduce the number of pinholes and other defects in the BOX layer. In later studies, it was found that a further high-temperature oxidation at over 13008C after high-temperature annealing results in the formation of a thermal oxide layer at the interface between the SOI layer and BOX layer at the same time as the oxidation of the SOI layer surface [13]. Typically, the BOX layer thickness is increased by about 40 nm. A substrate produced with this internal oxidation processing is referred to as an ITOX-SIMOX substrate. In this way, an SOI layer can be formed over an oxide layer of high quality, even on SIMOX substrates formed by oxygen ion implantation.
2.4.3.2 ELTRAN Substrates
Although thin-film SOI substrates for fine CMOS devices are categorized as either SIMOX substrates or wafer bonded substrates, as shown in Fig. 2.84. ELTRAN substrates are classified as BESOI (bond and etch-back SOI) substrates, a subdivision of the bonded substrate category. The BESOI substrate is produced by the growth of a two-layer structure that consists of the final layer that remains on the DW as the SOI layer and a layer that has a high etching speed by epitaxial growth followed by the formation of a thermal oxide layer on the surface and subsequent bonding to the HW. After that, most of the substrate is removed from the backside of the DW by grinding and polishing. Finally, the difference in etching speed is used to leave an SOI layer of good uniformity. The fabrication process for an SOI substrate produced by the ELTRAN method is shown in Fig. 2.86 [14]. First, a porous Si layer that comprises of two layers of different porosities is formed by anodization near the surface of the Si substrate on which the devices are formed (DW). After smoothening of the wafer surface by annealing in hydrogen to move the surface Si atoms, the layer that is to remain as the SOI layer is formed by epitaxial growth. After forming the layer that is to become the BOX layer by oxidation, the DW is bonded to the HW.
Next, a water jet is used to separate the DW and HW at the boundary of the two-layer porous Si layer structure. Finally, the porous Si layer is removed by selective chemical etching of the Si layer, hydrogen annealing is performed, and then the surface of the SOI layer is flattened to the atomic level. The ELTRAN method also uses epitaxial layer forming technology, so layer thickness controllability and uniformity of the layer that will become the SOI layer are obtained.
2.4.3.3 UNIBOND Substrates
The UNIBOND method features the introduction of the high controllability of ion implantation technology to wafer-bonded substrate fabrication technology [11]. The process of UNIBOND SOI
ELTRAN SiO2 SiO2 Si Epitaxial Si Double layered porous Si Formation of double-layered porous Si
Handle wafer Device wafer
Handle wafer Handle wafer
Device wafer Device wafer
Bonding Splitting of porous Si Water jet Etching and H2 annealing
FIGURE 2.86 Main process steps of ELTRAN.
substrate fabrication is shown in Fig. 2.87. Hydrogen ions are implanted to a concentration of about 1016 cm2in a DW on which a thermal oxide layer has previously been formed and then the DW is bonded to the HW. Then, after an additional annealing at low temperatures of about 4008C–6008C, separation from the hydrogen ion implanted layer occurs. The surface of the SOI layer is smoothened by light polishing to obtain the SOI substrate. By using ion implantation to determine the thickness of the SOI layer, controllability and uniformity are improved.
Here, three types of SOI substrates that have attracted particular attention have been introduced, but it is highly possible that in future, the SOI substrates will undergo further selection on the basis of productivity, cost, LSI yield, adaptability to large wafer diameters, and other such factors.
2.4.4
SOI MOSFET Operating Modes
SOI MOSFETs have two operating modes: the fully depleted (FD) mode and the partially depleted (PD) mode. The differences between these modes are explained using Fig. 2.88. For each operating mode, the cross sectional structure of the device and the energy band diagram for the region near the bottom of the body in the source–body–drain directions are shown.
For the FD device, the entire body region is depleted, regardless of the gate voltage. Accordingly, FD devices generally have a thinner body region than PD devices. For example, the thickness of the body region of a PD device is about 100 nm, but that of an FD device is about 50 nm. In the PD device, on the
UNIBOND
Oxidation and
H+ implantation
Touch polishing of SOI surfaces
Bonding at RT Annealing and
splitting Handle wafer
Handle wafer
Device wafer Device wafer Device wafer
SiO2 Si
H+
Si
FIGURE 2.87 Main process steps of UNIBOND.
FD or PD devices Source Drain EC EV Holes Source Drain EC EV Holes
Fully depleted NMOS Partially depleted NMOS
Si substrate Si substrate SiO2 SiO2 n+ n+ n+ n+ p n+ n+ n+ Neutral p region
FIGURE 2.88 SOI device operation modes.
other hand, the body region is only partly depleted and electrically neutral region exists. The presence of the region, focusing attention on the change in potential in the depth direction of the body region from the gate oxide layer, limits the gate field effect to within the body region, and the neutral region, in which there is no potential gradient, exists in the lower part of the body. Accordingly, the difference in potential between the surface of the body region and the bottom of the region is greater in a PD device than in an FD device, and the potential barrier corresponding to the holes between the source and body near the bottom of the body region is higher in the PD structure than in the FD structure. This difference in potential barrier height corresponding to the holes creates a difference in the number of holes that can exist within the body region, as shown in Fig. 2.88. These holes are created by impact ionization when the channel electrons pass through the high electric field region near the drain during n-MOSFET operation. The holes flow to the source via the body region. At that time, more holes accumulate in the body region of the PD structure, which has a higher potential barrier than the FD structure. This fact brings about a large difference in the floating body effect of the FD device and the PD device, determines whether or not a kink appears in the drain current–voltage characteristics, and creates a difference in the subthreshold characteristic, as shown in Fig. 2.89.
2.4.5
PD-SOI Application to High-Performance MPU
An example of a prototype LSI that employs PD-SOI technology and which was presented at the latest ISSCC is shown in Table 2.4. The year 1999 will be remembered as far as application of SOI to a high- performance MPUs is concerned. In an independently organized session at ISSCC that focused on SOI technology, IBM reported a 32-bit PowerPC (chip size of 49 mm2) that employs 250 nm PD-SOI technology [15] and a 64-bit PowerPC (chip size of 139 mm2) that employs 200 nm PD-SOI technology [16]. Samsung reported a 64-bit ALPHA microprocessor (chip size of 209 mm2) that employs 250 nm FD-SOI technology [17]. According to IBM, the SOI-MPU attained performance that was 20%–35% higher than an MPU fabricated using an ordinary bulk Si substrate. Furthermore, in the year 2000, IBM reported the performance of a 64-bit PowerPC microprocessor that was scaled down from 220 nm to 180 nm, confirming a 20% increase in performance [18]. In this way, the scenario that increased performance could be attained for SOI technology through finer design scales in the same way that it has been done for bulk Si devices when first established. IBM is attracting attention by applying these high-performance SOI-MPUs to middle-range commercial products, such as servers for e-business, etc., and shipping them to market as examples of the commercialization of SOI technology [19]. Sony,
No kink in FD Id−Vd characteristics 6.0e⫺03 5.0e⫺03 4.0e⫺03 3.0e⫺03 2.0e⫺03 1.0e⫺03 0.0e+00 5.0e⫺03 4.5e⫺03 4.0e⫺03 3.5e⫺03 3.0e⫺03 2.5e⫺03 2.0e⫺03 1.5e⫺03 1.0e⫺03 5.0e⫺04 0.0e+00 0 0.5 1 1.5 2 0 0.5 1 1.5 2
FD mode (VSUB=0 V) PD mode (VSUB=−15 V)
Drain voltage (V) Drain voltage (V)
Drain current (A) Drain current (A)
FIGURE 2.89 IdVdcharacteristics in FD and PD modes.
Toshiba, and IBM announced that they would employ SOI for the next-generation engine providing a high-performance platform for multimedia and streaming workloads, CELL [20]. Also, many manu- facturers who are developing high-performance MPUs have recently began programs for developing SOI-MPU. Currently, PD-SOI technology is becoming the mainstream in the high-performance MPU. The characteristics of PD-SOI and FD-SOI are compared in Table 2.5. In the high-performance MPU, improvement of transistor performance through aggressive increase in integration scale is an essential requirement, and PD-SOI devices have the merit that the extremely fine device design scenario and process technology that have been developed for bulk Si devices can be used without modification. Also, as described previously, because the PD-SOI can have a thicker body region than the FD-SOI (about 100 nm), those devices have the advantage of a greater fabrication margin in the contact-forming process and the process for lowering the parasitic resistance of the SOI layer. On the other hand, the PD-SOI devices exhibit a striking floating body effect, so it is necessary to take that characteristic into consideration in the circuit design of a practical MPU.
2.4.5.1 Floating Body Effect
PD-SOI structures exhibit the kinking phenomenon, as shown in Fig. 2.89, but IBM has reported that the most important factor in the improvement of MPU performance, in addition to reduction of the junction capacitance and reduction of the back gate effect, is increasing the drain current due to impact ionization. This makes use of the phenomenon in which, if the drain voltage exceeds 1.1 V, the holes that are created by impact ionization (in the case of an n-MOSFET) accumulate in the body region, giving the body a positive potential and thus lowering theVth
of the n-MOSFET, and thus increasing the drain current. The increase in drain current due to this effect is taken to be 10%–15%. On the other hand, from the viewpoint of devices for application to large-scale LSI, it is necessary to consider the relation between the MOSFET Vth and standby leak current.
According to IBM, even if there is a drop in Vth due to the
floating body effect, there is no need to preset the device Vth
setting for the operating voltage to a higher value than is set for
TABLE 2.4 PD-SOI Activities in ISSCC
Gate Length Performance Vdd Company Year
Logic
16 b Multiplier 300 nm 200 MHz 0.5 V Toshiba 1996
64 b ALU 130 nm 286 ns 1.2 V Intel 2001
32 b Adder 80 nm 1 ns 1.3 V Fujitsu 2001
54 b Multiplier 90 nm 8 GHz 1.4 V IBM 2005
64 b Execution unit 65 nm 4 GHz 1.1 V IBM 2006
Microprocessor 64 b PowerPC 200 nm 550 MHz 1.8 V IBM 1999 64 b PowerPC 180 nm 660 MHz 1.5 V IBM 2000 64 b PA-RISC 180 nm 1 GHz 1.5 V HP 2001 64 b Alpha-RISC 130 nm 1.45 GHz 1.2 V HP 2003 64 b Cell 90 nm 4 GHz 1.2 V IBM 2005 64 b Dual-Core 90 nm 2.6 GHz 1.35 V AMD 2006 DRAM=SRAM 16 Mb DRAM 500 nm 46 ns 1 V Mitsubishi 1997 128 Mb DRAM 165 nm 18.5 ns 3.3 V Toshiba 2005 64 kb SRAM 65 nm 5.6 GHz 1.2 V IBM 2006 TABLE 2.5 FD vs. PD FD PD Manufacturability þ Kink effect þ Body contact þ Vthcontrol þ
SCE (scaling ability) þ Parasitic resistivity þ
Breakdown voltage þ
Subthreshold slope þ Pass gate leakage þ History dependence þ
bulk Si devices in the worst case for the increase in the standby leak current, which is to say, transistors that have the shortest gate lengths at high temperatures [15].
Next, consider the pass gate leak problem [15,21], which is shown in Fig. 2.90. In the case of an n-MOSFET on SOI, consider the state in which the source and drain terminals are at the high level and the gate terminal is at the low level. If this state continues for longer than 1ms, for example, the body potential becomes roughly VsVbi (where Vs is the source terminal voltage andVbi is the built-in
potential). In this kind of state, the gate voltage is negative in relation to the n-MOSFET source and drain, and holes accumulate on the MOS surface. If, in this state, the source is put into the low level, the holes that have accumulated on the MOS surface become surplus holes, and the body–region–source pn junction is biased in the forward direction so that a pulsed current flows, even if the gate is off. Because this phenomenon affects the normal operation of the access transistors of DRAM and SRAM and the dynamic circuits in logic LSIs, circuit design measures such as providing a margin for maintenance of the signal level in SRAM and dynamic logic circuits are required. For DRAM, it is necessary to consider shorter refresh frequencies than are used for bulk Si devices.
Finally, we will describe the dependence of the gate delay time on the operating frequency, which is called the history effect [15,22]. As previously described, the body potential is determined by the balance between charging due to impact ionization and discharging through the body–source pn junction diode, and a change in that produces a change in the MOSFETVthas well. For example, consider the pulse