In this section, we discuss ROMs that are programmable. They are generally known as nonvolatile read=write (NVRW) memory. They pose the nonvolatile property of the mask-programmed ROM and the read=write property of SRAM and DRAM. This nonvolatile read=write property makes them attractive for a wide range of applications. EPROM, EEPROM, and flash memories are examples of NVRW memory. The basic architecture of NVRW memories is identical to that of the ROMs. The memory core consists of a transistor matrix. An active special MOS transistor exists at the cross-point of every row and a data line (column). This transistor has an adjustable threshold voltage that can be electrically changed. All the three EPROMs mentioned above use a transistor with a floating gate to trap negative charges to change the transistor threshold voltage so that the device can be programmed to store a ‘‘1’’ or a ‘‘0.’’
The schematic of a floating gate transistor used as an EPROM cell is shown in Figure 5.17 [10]. This special transistor is called floating gate avalanche injection MOS (FAMOS). Almost all nonvolatile semiconductor memories use some form of the floating gate transistor for information storage. The cell is basically an enhancement type n channel MOSFET with two gates made of polysilicon. This transistor is fabricated using a double poly process. The first-level poly is used to create a gate that is floating, i.e., it is not connected to anything. The floating gate is electrically isolated and surrounded by silicon dioxide. The second gate is made up of the second poly and is electrically coupled to the row or word line and functions in the same way as the gate of a regular enhancement MOSFET. The floating gate, which is made up of poly 1 and surrounded by silicon dioxide, is used for trapping negative charge. The trapped negative charge in the floating gate will increase the threshold voltage of the transistor above VDD. If there are no negative charges trapped in the floating gate, the transistor will have
A0 A1 Decoder R1 D1 D2 D3 D4 R2 R3 R4 VDD VDD VDD VDD A0 0 0 1 1 0 1 0 1 A1 0 1 1 1 R1 1 0 1 1 R2 1 1 0 1 R3 1 1 1 0 R4 1 0 0 1 D1 1 1 1 0 D2 1 1 0 0 D3 0 0 1 1 D4
FIGURE 5.16 A 434 NAND-based ROM array.
the normal threshold voltage of an NMOS transistor. In simple words, the transistor can have two different threshold voltages depending on the charge on the floating gate. If there are charges trapped in the floating gate, the transistor will have high threshold voltage, which will be greater thanVDD, and if
there are no charges trapped in the floating gate the transistor will have a normal threshold voltage. This property can be used to connect or disconnect the transistor to the bit line (Figure 5.14c). When a ‘‘1’’ needs to be stored, the transistor threshold voltage will be adjusted to be aboveVDDby trapping negative
charges on the floating gate so that when the appropriate row (word line) is selected the transistor will not turn ON. The word line voltage (VWL) will be less than that of the new threshold voltage (Figure
5.17c). This is similar to the scheme outlined in Figure 5.14c. When a ‘‘0’’ needs to be stored, the transistor threshold voltage is not raised and when the appropriate row is selected, the transistor will turn ON and pull the bit line to ground. The transistor will retain the modified threshold voltage for a long time even when the supply voltage is turned OFF. To write a new set of data into the memory core, the programmed values must be erased, after which new programming (writing new data values) can be done [8].
The transport of charge through the oxide layer is the basic mechanism that makes possible charging and discharging of the floating gate, which in turn enables us to modulate the threshold voltage of the MOS transistor. To achieve the programming operations, the negative charge must move across the potential barrier built by the insulating layers between the floating gate and the other terminals of the device. There are two mechanisms by which negative charge can be trapped in the floating gate; they are channel hot electron (CHE) injection and Fowler–Nordheim (F–N) tunneling.
Hot electron injection occurs when electrons are accelerated using high electric fields to high enough energy levels to overcome a barrier. Floating gate transistors can be programmed using hot electron injection. For programming the FAMOS transistor, a large voltage is applied between its drain and the source; at the same time a larger voltage is applied to its control gate. The voltage applied at the control gate must be greater than the drain voltage [2]. The voltage applied between the drain and the source terminals will accelerate the electrons as they move through the channel. These electrons are called hot electrons because they acquire high energy by the time they reach the drain of the transistor. The electric
First-level polysilicon (floating gate) Second-level polysilicon (control gate) (a) (b) G S D n+ n+ (c) VWL VGS “ON” “OFF” ID
FIGURE 5.17 (a) Cross section of a floating gate transistor used as an EPROM storage cell. (b) Circuit symbol of a floating gate transistor. (c) Threshold voltage shift of the FAMOS transistor due to trapped electrons in the floating gate (the diagram is not drawn to scale). (From Martin, K.,Digital Integrated Circuit Design, Oxford University Press, New York, 2000. With permission.)
filed established due to the large, positive potential applied at the control gate will accelerate these hot electrons to the floating gate. Since the floating gate is surrounded by silicon dioxide, under normal conditions, the trapped electrons will remain in the floating gate. Hot electron injection can occur with oxides as thick as 100 nm, which makes it relatively easy to fabricate the device [8].
Tunneling is defined as a quantum mechanical process in which a particle can pass through a classically forbidden region. In the case of semiconductor memories, tunneling can be visualized as a process that allows electrons to pass from the conduction band of one silicon region to that of another through a thin layer of silicon dioxide [2]. In F–N tunneling, tunneling of the electrons to floating gate can occur without drain current. Here, the drain and the source are typically kept at 0 V. For tunneling to occur, the thickness of the oxide separating the floating gate from the drain region must be very thin, of the order of 10 nm or less. Figure 5.18 shows the cross section of an early modified FAMOS transistor called a floating gate tunneling oxide transistor (FLOTOX). A high value of electric field, typically of the order of 107V=m, is needed across the oxide for programming the FLOTOX device. This field can be achieved by applying a 10 V potential across an oxide of 10 nm thickness. This field is large enough for the electrons to tunnel through the thin oxide to the floating gate, which enables the programming of the FLOTOX device. The main advantage of the F–N tunneling programming approach is that the tunneling is reversible, i.e., erasing is simply achieved by reversing the voltage at the control gate [8]. Figure 5.19 shows the FLOTOX device F–N tunnelingI–Vcharacteristic. Another major advantage of F–N tunneling over hot electron injection is that large drain currents are not required. This makes it much easier to generate the high voltage required for programming using an on-chip charge pump circuit [10]. The main differences among the three EPROMs are in the methods of erasing. To reprogram the EPROM, first the data that is already programmed into the chip must be erased. This is done by illuminating the EPROM cell with ultraviolet (UV) rays. The UV light imparts energy to the trapped electrons in the floating gate and these high-energy electrons will be able to escape through the oxide back to the substrate. The EPROM chips must be packaged in ceramic casings that have quartz windows over the chip to facilitate for the UV exposure. This is one of the drawbacks of the EPROMs because the ceramic packages are often expensive. Another drawback of EPROMs is that they must be removed from the circuit for reprogramming. The whole EPROM has to be erased for reprogramming since they do not have the ability to selectively erase memory locations [2]. Thin oxide region for F−N tunneling Control gate Floating gate n+ n+
FIGURE 5.18 Cross section of the FLOTOX transistor that uses Fowler–Nordheim (F–N) tunneling for charge transfer to floating gate.
I
–10 V
10 V
VGD
FIGURE 5.19 Fowler–Nordheim tunneling I–V characteristic of a FLOTOX transistor. (From Rabaey, J.M., Chandrakasan, A., and Nikolic, B.,Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall, Englewood Cliffs, NJ, 2003. With permission.)
The EEPROM eliminates most of the drawbacks of EPROM. It can be erased as well as programmed elec- trically. That means an EEPROM neither needs an expen- sive ceramic quartz window type packaging nor needs to be removed from the circuit for programming and eras- ure. A FLOTOX type device shown in Figure 5.18 or close variations that use F–N tunneling for programming and erasure are used in EEPROMs. EEPROMs need only one external power supply as the high voltages needed for programming are generated internally using charge pumps. In most EEPROMs, write and erase operations are done on a byte per byte basis. EEPROMs are based on a two transistor memory cell shown in Figure 5.20. Each cell has a FLOTOX device in series with a regular N- channel enhancement transistor. The FLOTOX transistor is used for information storage and the regular NMOS is used for the cell access during a read operation. During a normal read operation, the gate of the FLOTOX device is held atVDDand the word line connected to the NMOS
gate is used for individual cell selection. EEPROM cells that consist of two transistors (FLOTOX and the regular NMOS) are larger than the EPROM cells. Also FLOTOX
devices are larger than the FAMOS transistors used in EPROMs. Hence EEPROM-based memory chips pack fewer bits at higher cost than the EPROM-based memory chips [8].
Flash memories combine the flexibility of EEPROM and the high density of EPROMs. Its storage cell has only one transistor. In terms of cost and flexibility, it lies somewhere between the EPROM and the EEPROM (see Figure 5.21). Some flash technologies use hot electron injection to program the devi- ces whereas others use F–N tunneling mechanism to program the devices. All types of flash memories use F–N tunneling for erasure. As discussed earlier, the F–N tunneling directly adds or removes all charge to or from the floating gate. This results in a low current program and erase cycles, which translate into high efficiency and low-power operation. Unlike EEPROM, flash memories are erased and programmed in blocks consisting of multiple locations. The density and flexibility advantages of flash memories over EEPROM have made them very attractive for a wide range of applications such as digital
Word line
Bit line
VDD
FIGURE 5.20 A 2-transistor EEPROM cell consisting of a FLOTOX device and a regular NMOS transistor. (From Rabaey, J.M., Chandra- kasan, A., and Nikolic, B.,Digital Integrated Cir- cuits: A Design Perspective, 2nd ed., Prentice Hall, Englewood Cliffs, NJ, 2003. With permission.)
Cost 2T/cell EEPROM Flash EPROM ROM 1T/cell 1T/cell
Byte rewrite capability. Electrically programmable and erasable in system Electrically programmable and
erasable in system Electrically programmable; not electrically erasable
Not electrically programmable Flexibility
FIGURE 5.21 Comparison of nonvolatile memories. (From Campardo, G., Micheloni, R., and Novosel, D.,VLSI Design of Non-Volatile Memories, Springer-Verlag, Heidelberg, Germany, 2005. With permission.)
audio players, digital cameras, and mobile phones. Flash memory is also used in USB flash drives for general storage and transfer of data between computers replacing the floppy disks.
There are several different flash technologies based on different flash memory cells. Some of the widely used flash memory cells are NOR flash cell, NAND flash cell, AND flash cell, and divided bit line NOR (DINOR) flash cell. Flash memories are currently available in a variety of densities, operating voltages, packages, and operating temperatures. They are also available in a variety of block sizes. The block size relates directly to the average size of each data sample of file storage requirements in the flash memory– based design. The use of smaller blocks may require more on-chip circuitry to decode and effectively isolate one block from all others, which can impact the die size and cost [2]. A detailed analysis of flash memories can be found in Ref. [2]. Figure 5.22a gives the unit cell comparison between the NOR- and the NAND-type cells [2]. Figure 5.22b gives a comparison of commonly used flash memory cell structures, program method, erase method, layers, and manufacturing companies for NOR, DINOR, AND, and NAND devices [2]. Currently, the two most common flash architectures are NOR- and NAND-based devices. NOR-based devices are mainly used for program and data storage applications and the NAND-based devices are mainly used for mass storage applications such as the memory cards and the solid-state disk drives.
NOR type NAND type
Control gate Control gate
Floating gate Poly/poly dielectric Floating gate
Tunnel oxide Tunnel oxide P-substrate (a) P-substrate n+ n− n+ n+ n+ n+ Technology Structure Program method Erase method Layers Company BL
NOR DINOR AND NAND
WL1 WL2 WL3 CHE F−N F−N F−N F−N F−N F−N F−N 2P2M 3P2M 3P2M 2P1M
Intel, AMD Mitsubishi Hitachi SamsungToshiba
SGL S-BL L-DL GSL SSL BL BL ST1 BL (b)
FIGURE 5.22 (a) Unit cell comparison between the NOR and NAND type cell. (b) A comparison of commonly used flash memory cell structure layouts, program method, erase method, layers, and manufacturing companies for NOR, DINOR, AND, and NAND devices. (From Sharma, A.K.,Advanced Semiconductor Memories: Architectures, Designs, and Applications, IEEE Press and Wiley Interscience, New York, 2003. With permission.)