Criteris d’Impacte Social

Flash-based FPGAs, differently from OTP FPGAs (Section 3.1), are reprogrammable devices in which the configuration is held by a flash-based infrastructure. Basically, the user logic contained in the FPGA is interconnected to obtain the desired architecture through a routing network im-plemented with flash-based switches [236]. Since the configuration is stored exploiting a flash

Figure 3.7: Missions explointing Microsemi RTAX-S/SL FPGAs

technology, this kind of FPGA is able to be Live At Power-Up (LAPU). In other words, the FPGA can be switch-off without losing the internal configuration.

The unique vendor that offers space-grade flash-based FPGAs is Microsemi with the Mi-crosemi RT ProAsic FPGA family [40] [139]. In this FPGA family the configuration is stored re-sorting to an advanced flash-based 130 nm LVCMOS process [202] with 7 layer of metal.

A key aspect of the Microsemi RT ProAsic FPGAs configuration infrastructure is the so-called Flash*Freeze technology [139]. This technology is able to completely shut down the dynamic power consumption, while retaining FPGA memories and registers content, without the need of switching off the system clock and related distribution network. To ease the power management in the design, the user can quickly switch on and off the Flash*Freeze mode (i.e., in less than 1µs) by driving a dedicated FPGA pin. Thanks to this features, this kind of FPGAs is able to reduce the dynamic power consumption by 40% and static power consumption by 50% w.r.t. other FPGA technologies.

The user logic in Microsemi RT ProAsic FPGAs, differently from the configuration infrastruc-ture, is implemented using standard CMOS technology. The basic element composing the user logic is the VersaTile [139]. Each VersaTile, as shown in Figure 3.8, can be configured in order to implement: all 3-input combinatorial functions, a latch with clear or set, a D-type flip-flop with clear or set, or Enable D-type flip-flop with clear or set.

Moreover, each VersaTile is equipped with nine VersaNets. A VersaNet is an element allowing a minimum skew distribution of the clock signal, or a minimum delay communication among VersaTiles composing a combinatorial network with high fanout.

Figure 3.9 shows the chip-level architecture of Microsemi RT ProAsic FPGAs. It can be noted

(a) 3-input combinatorial function

(b) D-type flip-flop (c) Enable D-type flip-flop

Figure 3.8: VersaTile configurations [139]

Figure 3.9: Chip-level architecture of Microsemi RT ProAsic FPGAs [139]

that in addition to VersaTiles and the management unit for the Flash*Freeze technology, Mi-crosemi RT ProAsic FPGAs contains:

• Clock Conditioning Circuitries (CCCs)

• Advanced I/O modules (Pro I/Os)

• RAM blocks

• User non-volatile Flash ROM.

Six CCCs are contained in every Microsemi RT ProAsic FPGA. Each CCC is equipped with a configurable Phase Locked Loop (PLL) [11], that allows designers to generate a custom clock fre-quency starting from an input clock reference. The frefre-quency of the generated clock signal must

be in the 0.75-250 MHz range, while the input input clock reference in the 1.5-250 MHz range.

From these data it is possible to understand that the maximum operating frequency of a design implemented in the Microsemi RT ProAsic FPGA is 250 MHz. Moreover, CCCs are equipped with sophisticated control circuitry ensuring to minimize the jitter and vary the phase of the generated signal. Eventually, the location of CCCs (four located at the FPGA corners, and two at the mid left and right FPGA side, see Figure 3.9) minimizes the skew associated with the clock distribution.

Advanced I/O modules provide a flexible management of I/O interfaces. In fact, they supports different voltages (i.e., 1.2, 1.5, 1.8 and 2.5 V), and a plenty of I/O standards (i.e., single-ended, differential, voltage-referenced), enabling a great adaptability of these FPGA to different commu-nication links.

RAM blocks provide on-chip memory resources to the designer. These blocks can be pro-grammed to support a variable aspect-ratio, that must not exceed the available storing resources in a bank (i.e., 4,608 bits). Each module has an independent read and write port in which the port width can be independently configured. Moreover, RAM blocks are equipped with a FIFO control unit that enables the implementation of a FIFO buffer without wasting VersaTiles. This control unit is fully customizable to implement different FIFO lengths and FIFO control signals configurations. Obviously, to implement high sized FIFO buffers different RAM blocks can be cascaded.

User non-volatile Flash ROM is a peculiar resource of Microsemi RT ProAsic FPGA (i.e., FPGAs based on other technology do not contain this kind of resource). This kind of resource can be re-ally useful for designers especire-ally when modules composing the developed system requires fixed configurations (e.g., Internet protocol addressing, Device serialization and/or inventory control, etc.). The Flash ROM size is limited to 1 kbit, and its content can be just modified at design time through a Joint Test Action Group (JTAG) programming interface, but can be read back via direct FPGA core addressing.

By comparing the internal architecture of Microsemi RT ProAsic and Microsemi RTAX-S/SL FPGAs, it can be immediately noted that the former do not provide SEU-hardened components.

For these reasons, designers are in charge of applying SEU mitigation techniques (Section 3.4) depending on the flight-critical nature of the application.

Table 3.1 compares the available resources between the RT3PE3000L [139] and RTAX4000S/SL [141]. These two FPGAs are the biggest devices of the Microsemi RT ProAsic and Microsemi RTAX-S/SL FPGA families, respectively. In order to perform the comparison of the available user logic, the total amount of R-cells and C-cells in the RTAX4000S/SL must be sum, since each VersaTile of the RT3PE3000L can be configured both as a register or combinatorial function. Moreover, it must be noted that C-cells are more efficient than VersaTile when configured as combinatorial function, since the former are able to implement 5-input combinatorial functions, while the lat-ter just 3-input ones. Aflat-ter these considerations, it can be depicted that the available user logic is almost the same in the considered devices. However, some advantages in favour of the Microsemi

Table 3.1: Comparison of RT3PE3000L and RTAX4000S/SL internal resources

RTAX-S/SL family still remain, since the registers in these FPGAs are already SEU-hardened by de-sign, while in Microsemi RT ProAsic FPGAs hardening techniques must be applied wasting user logic.

The Embedded RAM/FIFO resources are almost the same in both devices, and Microsemi, as for the space-grade OTP FPGAs (Section 3.1), provides an EDAC IP-core [140] to protect RAM blocks against particles induced effects. Thus, no differences on the volatile memory resources can be appreciated between the two considered FPGAs. The same consideration can be done for the I/Os.

The main advantages provided by the Microsemi RT ProAsic FPGAs is the higher level of flex-ibility. In fact, differently from the Microsemi RTAX-S/SL family, Microsemi RT ProAsic FPGAs are reconfigurable and they embed configurable CCCs allowing multi-clock domains design without requiring external devices (e.g., PLLs). Moreover, as aforementioned, the Microsemi RT ProAsic FPGAs are the only FPGAs equipped with a Flash ROM module.

About the configuration layer, the flash-based technology exploited in Microsemi RT ProAsic FPGAs is immune to SEU effects, so no mitigation techniques must be applied on the configura-tion memory .

Thanks to the advantages concerning the flexibility, Microsemi RT ProAsic FPGAs are currently used on the International Space Station (Figure 3.10(a)) [153], and it has been successfully used in two NASA missions: the Interface Region Imaging Spectrograph (IRIS, Figure 3.10(b)) [152], and LADEE Lunar Atmosphere and Dust Environment Explorer (Figure 3.10(c)) [156]