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Differently from OTP (Section 3.1) and Flash-based (Section 3.2), SRAM-based FPGAs are repro-grammable devices that lose their configuration when are powered-off, since the configuration layer is implemented through a volatile memory (SRAM memory). For this reason, to properly work these devices require an external non-volatile memory storing the configuration needed to program the FPGA at power-up.

(a) International Space Station (b) IRIS

(c) LADEE Lunar Orbiter

Figure 3.10: Missions explointing Microsemi RT ProAsic FPGAs

The main vendor offering space-grade SRAM-based FPGAs is Xilinx [99]. Figure 3.11 shows the Xilinx space-grade FPGAs roadmap.

Figure 3.11: Xilinx space-grade FPGAs roadmap

As can be noted the actual state-of-the-art architectures are the Xilinx Virtex 4 QV [225], and Xilinx Virtex 5 QV [228] families.

The main difference between these two families is the Rad-Hardened By Design (RHBD) fea-ture of the Xilinx Virtex 5 QV family. In Xilinx Virtex 5 QV FPGAs both the configuration memory and the internal registers (i.e., user logic and I/O registers) are rad-hardened by design against SEUs. Basically, the rad-hardness against SEUs is obtained exploiting dual-node latches ap-proach that provide nearly 1,000 times the SEU hardness of the standard cell latches.

Another main difference concern the CMOS technology. In fact, Xilinx Virtex 4 QV FPGAs make use of the 90 nm Copper CMOS process, Xilinx Virtex 5 QV FPGAs the 65 nm Copper CMOS one. This difference allows to slightly boost up the speed performance in Xilinx Virtex 5 QV family from 400 MHz (i.e., the maximum operating frequency of Xilinx Virtex 4 QV FPGAs) to 450 MHz.

The basic elements composing the user logic in these two families is the Slice. Figure 3.12 highlights the differences in the Slice internal structure between the two families.

(a) Xilinx Virtex 4 QV Slice (b) Xilnx Virtex 5 QV Slice

Figure 3.12: Comparison of Slice internal structure

It can be noted that Xilinx Virtex 4 QV FPGAs embeds smaller Slices than Xilinx Virtex 5 QV FP-GAs. Just two registers (Rs) and two Look-Up Tables (LUTs) are present in the Xilinx Virtex 4 QV Slice. Moreover, Xilinx Virtex 5 QV Slice provides 6-input LUTs (LUT6, i.e., these LUTs can be also configured as two 5-input LUTs, during synthesis, to increase the efficiency), while Xilinx Virtex 4 QV Slice just 4-input LUTs (LUT4). Concerning the other Slice resources the two family are equivalent.

Internally, slices are grouped in Configurable Logic Blocks (CLB). In Xilinx Virtex 4 QV family four Slices compose a CLB, instead in Xilinx Virtex 5 QV one just 2 Slice are required. Every CLB integrates internal fast interconnect and connects to access general routing resources.

The routing resources in space-grade Virtex families is provided through General Routine Ma-trix (GRM) or direct connection among CLBs. A GRM is an array of routing SRAM-based switches implemented in the aforementioned rad-hardened technology. Figure 3.13 shows the intercon-nections between GRM and CLB.

Figure 3.13: Xilinx Virtex FPGAs routing infrastructure

Each GRM provides connections to other GRMs through a North, East, South or West -side link, plus a direct connection to the closest CLB. Moreover, to increase the interconnection capabil-ity, CLBs are equipped with a direct connection to the left and right -side CLBs, plus a feedback connection to provide a loop-chain among internal LUTs. This routing infrastructure ensures a minimum delay for both short (through direct connections) and long (through GRMs) connec-tions.

In addition to CLBs and GRMs, the internal architecture of space-grade Xilinx Virtex FPGAs is composed by four other components:

• Block RAM (BRAM)

• Clock Management Tile (CMT)

• Extreme Digital Signal Processor (DSP48E)

• High-performance parallel SelectIO bank.

BRAMs are configurable true dual-port SRAM memory blocks, so each memory port can be used in both write or read mode. Each BRAM is able to work up to 360 MHz, and is 36 kbit in size, but can be also used as two separate block of 18 kbit. The write/read port size can span from 1 bit width up to 36 bits width, for true dual-port memory, or 72 bits, for simple dual-port memory (i.e., one port used in write mode and one in read mode). BRAMs embed control logic to operate as FIFO buffer, also. This control unit is fully customizable to implement different FIFO lengths and FIFO control signals configurations. Moreover, each BRAM has a dedicated cascade

routing, that allows to reach high performance when more than one BRAM must be used to build a big memory block. Eventually, as in space-grade OTG and Flash-based FPGAs, there is an Error Correcting Code (ECC) to mitigate SEU effects.

CMT provide the most flexible and highest-performance clock management for FPGAs. Each CMT integrates two Digital Clock Managers (DCM) and one PLL. A DCM is a digital device that together with the PLL is able to perform clock distribution delay compensation, clock multipli-cation/division, coarse-/fine-grained clock phase shifting, and input clock jitter filtering.

DSP48Es are modules containing a 25x18 multiplier (in Xilinx Virtex 5 QV FPGAs) or a 18x18 multipler (Xilinx Virtex 4 QV FPGAs), plus a 48 bits accumulator for Multiply-And-Accumulate (MAC) operations. Moreover, they contain dedicated links among them in order to create cascade connections useful to implement high-performance arithmetic and digital signal processing op-erations, without wasting user logic resources. However, these components are not rad-hardened by design, so designer must apply SEU mitigation techniques on them.

High-performance parallel SelectIO banks support different voltage levels (i.e., 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V), and a plenty of I/O standards (i.e., single-ended, diffential, voltage-referenc-ed), that enables a great adaptability of these FPGAs to different communication links. Each bank contains input/output registers, rad-hardened by design, that can operate in both Single Data Rate (SDR) or Double Data Rate (DDR) modes. Moreover, they contain Per-bit deskew circuitry allowing for programmable signal delay internal to the FPGA. Per-bit deskew flexibly provides fine-grained increments of delay to carefully produce a range of signal delays. This is especially useful for synchronizing signal edges in source-synchronous interfaces [37].

In order to perform a comparisons with other space-grade FPGA technologies (presented in Sections 3.1 and Section 3.2), Table 3.2 shows the internal resources of the two biggest FPGAs of the Xilinx Virtex 4 QV (i.e., Xilinx Virtex 4-QV XQR4VLX200 [225]) and Xilinx Virtex 5 QV (i.e., Xilinx Virtex 5-QV XQR5VFX130 [228]) families.

Table 3.2: Comparison of Xilinx Virtex 4-QV XQR4VLX200 and Xilinx Virtex 5-QV XQR5VFX130 internal resources

In order to properly compare these two FPGAs, one must remember that XQR4VLX200 FPGA is not rad-hardened by design, so all the internal resources must be protected through the