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One-Time-Programmable (OTP) FPGAs are devices that can be just programmed once and then are able to maintain the configuration also at power-off. This is possible since in these devices

the configuration is hold by an antifuse metal layer.

The unique family of OTP FPGAs that is space-qualified is the Microsemi RTAX-S/SL [41] [141].

In these FPGAs the user logic and the configuration layer are split in two different layers. In par-ticular, the configuration layer is a metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 3.1). The antifuse connections are

Figure 3.1: Configuration layer in Microsemi RTAX-S/SL FPGAs [141]

usually open and when are programmed compose a low-impedance interconnection among the different metal layers. The low impedance nature of this interconnection ensures to reach very high communication speed.

Moreover, the metal-to-metal antifuse programmable interconnect element does not occupy sil-icon area in the user logic layer, making possible the sea-of-modules architecture. As shown in Figure 3.2, this kind of architecture ensures to fully exploit the silicon area without wasting space for the routing resources.

In particular, the user logic layer is composed of two basic elements: R-cell and C-cell.

The former is a register hardened against SEUs triple redundancy to achieve a Linear Energy Transfer (LET) threshold of greater than 60MeV − mg /cm²[141]. The triplication is obtained by inserting three master-slave latch pairs in which the three outputs of the master and slave side are majority voted in order to apply the fault tolerant technique. In order to avoid fault accumulation, each master-slave latch is equipped with a feedback that, in case of fault, restore the correct value in the latch. Moreover, during the floorplan of the user logic layer, the location of the three pairs of master-slave latches is defined to avoid that a single ion induces a SEU in more than one latch.

For the sake of completeness, Figure 3.3 shows the difference between a standard R-cell (Figure 3.3(a)) and its SEU-hardened version (Figure 3.3(b)).

Figure 3.2: Comparison of the user logic layer between common FPGA and sea-of-modules ar-chitectures [141]

(a) Standard R-cell (b) SEU-hardened R-cell

Figure 3.3: R-cell comparison [141]

The C-cell is a combinatorial block able to implement up to 4,000 5-input combinatorial func-tions. In addition, this cell is equipped with a dedicated carry logic for improving the perfor-mance of arithmetic functions.

Internally to the Microsemi RTAX-S/SL FPGA, an R-cell is packed together with two C-cells, two Transmit (TX), and two Receive (Rx) routing buffers inside a Cluster. A couple of Clusters composes a SuperCluster (Figure 3.4). Moreover, each SuperCluster contains a Buffer used to minimize system delays when high fanout logic functions are implemented combining different

SuperClusters.

Figure 3.4: SuperCluster internal architecture [141]

Thanks to the modularity of the internal architecture, during synthesis the user defined architec-ture can be fine-grained split among SuperClusters and their internal elements, allowing to reach high performances and a fast design flow.

Figure 3.5 shows the chip-level architecture of Microsemi RTAX-S/SL FPGAs. It can be noted

Figure 3.5: Example of an Microsemi RTAX-S/SL FPGA chip level architecture [141]

that the chip is composed of different Core Tiles, each Core Tile contains a lot of SuperClusters, plus a certain amount of SRAM blocks. The number of SuperClusters and SRAM blocks change depending on the selected FPGA, more detailed information are provided in [141].

Each SRAM block is 4,608 bits in size. However, the designer can freely configure these storage elements, both in terms of aspect ratio and read/write port width, depending on its needs. More-over, each SRAM block contains a First In First Out (FIFO) control unit [201], allowing the design

of FIFO buffers without wasting C-cells inside SuperClusters. As well as SRAM blocks, a FIFO can configured in terms of depth (if the required depth exceeds the storage elements contained in a single SRAM block, the FIFO is implemented concatenating different blocks) and control signals (i.e., EMPTY, ALMOST EMPTY, FULL and ALMOST FULL [201]).

Since SRAM blocks are not rad-hardened by design, if the developed system must work in an environment characterized by high energy particles, two mitigation techniques can be easily ap-plied. The former is an Error Detection and Correction IP-core (CoreEDAC [140]), already devel-oped by Microsemi, that can be directly connected to the storage element to be protected. The latter is a scrubbing IP-core, integrable in the aforementioned CoreEDAC IP-core, that ensures the data integrity while the memory block is not used through a memory scrubbing approach [183].

Eventually, the chip-level architecture of Microsemi RTAX-S/SL FPGAs (Figure 3.5) is com-pleted by I/O structures. The flexible nature of I/O structures allows designers to apply mixed-voltage configurations of input and output pins. Each I/O structure can be programmed to work in different operational modes, i.e., single-ended, differential-ended and voltage-referenced. This flexibility enables to support a lot of different communication standards.

The I/O structures are organized in I/O clusters (Figure 3.6), each containing two I/O modules, four RX modules, two TX modules, and a buffer (B) module [141]. Each I/O module is composed of an input register, an output register, and an enable register. All of these registers are hardened against SEU with the same mitigation technique used in R-cell [141].

Figure 3.6: I/O cluster internal architecture

After the internal architecture analysis, it can be noted that Microsemi RTAX-S/SL FPGAs pro-vide a lot of already implemented fault-mitigations techniques against SEUs. For these reasons in the last years this kind of FPGAs have been extensively used by space agencies both on satellite, working in the Low Earth Orbits (LEOs), and spacecraft, involved in space exploration missions.

Figure 3.7 shows some examples of the missions in which these FPGAs have been used.