For HL-LHC running, both the front-end electronics [36] and the trigger/DAQ pre-processors Tile Calorimeter Pre-Processors (TilePPRs)[37] have been redesigned, and allCOTScomponents have undergone a program of extensive radiation testing with ionising radiation (Co60), protons at a medi- cal facility, and neutrons from a reactor. Additional redundancy is introduced in the signal processing andLVPSchains. The most dramatic change is to send the data from all Tile cells off-detector by high-speed fibre optic links. The new signal chain is shown in Fig. 28. The 3-in-1 amplifier/shaper card of the current system will be replaced by one of three alternatives under study. AMotherboard (MB) routes the high-speed signals to aDaughter-board(DB) [38], and the MB also distributesLV and handles slow controls. Since all data is sent off-detector for each event, there is no longer a need for analog fast trigger lines since theL0tower trigger can be formed at the back-end pre-processor using the digital cell data.
It is possible that the current front-end shaping will not be optimal for the high pile-up environ- ment. In order to study this, as well as test all the new electronics, a "hybrid demonstrator" prototype has been constructed. This device is an exact prototype of the Phase-II drawer, but with the addition of backwards-compatible analog trigger cables so that it can be used in the current detector. Recent tests of a demonstrator has obtained performance superior to that of the current system and has permitted more accurate costing and design of mechanical tooling. ACharge-injection-Scan (CiS) from the demonstrator, shown in Fig.29, shows linearity of 0.5 parts per mil, an order of magnitude better than the current system.
To facilitate easier extraction and replacement for repair, particularly considering the high radi- ation doses, the mechanical drawer system will be replaced with shorter "mini-drawers" supporting 12 PMTs (the current drawers support 24 PMTs). Prototypes for these mini-drawers have been manufactured for the hybrid demonstrator as shown in Fig.30.
TheLVPSsystem consists of +10 V feeder supplies located at the ends of the barrels, as shown in Fig.31. Point of load regulators (POLs)are used on the MB and DB to supply the needed voltages. Each MB and DB is functionally separated into halves, with each half processing the photo-tubes from one side of the wedge. Each half has a separate LV feed that could power both halves (by means of a diode OR) of a mini-drawer if one feed fails.
The DB controls all communication with the back-end electronics. TheDaughter-board (DB)also receives slow control commands from theTilePPRand routes it to theMotherboard (MB). Each half
Figure 29.(left) OneCiSpulse shape. (right) Pulse height versusCiSpulse amplitude.
Figure 30. One new mini-drawer used in the demonstrator; the analog trigger adder card will not be present in the Phase-II system.
DBis controlled by a Kintex-7FPGA, as shown in Fig.32. TheMBsends the digitised signals from thePMTsto theFPGAson theDBby means of a 400-pin SAEF connector; theFPGAthen sends the data to the back-end electronics by means of optical fibres.
A modulator-based [39] Quad Small Form-Factor Pluggable (QSFP)optical module is used to drive the fibres at 4.8 Gbps upload- and 10.24 Gbps download speeds. While the CERNGBT[40]
Figure 31.Power distribution scheme.
protocol is programmed in the FPGAto handle error correction of the data stream, the only GBT product employed in the system is theGBTx ASICwhich generates a stableTTCbeam clock; it is also used to remotely re-flash the firmware when necessary. All other communication with the back- end TilePPR is accomplished in the Xilinx "GTX" layer of the Kintex7 FPGA. Commercial optical modulators instead of versatile-link driver/receivers have been chosen for cost-effectiveness, small PCBfootprint, and the demonstrated radiation hardness of this technology. Modulators also permit the possibility of sending the data at higher rates in the future.
Figure 32.Signal flow in the Daughter Board (version 3).
simply to redesign the 3-in-1 with new discreteCOTScomponents. With this card, the 12-bit digi- tisation must reside on the MB. The other alternatives are customASICs shown in Fig. 33. It is possible that the small feature sizes (65 or 130 nm) could be very radiation tolerant, and that the noise might be lower, particularly if the ADCis incorporated in the ASIC. With the lower voltage used in these technologies, it will be necessary to have more than two gain ranges. The"Charge Integrator and Encoder" ASIC (QIE)[41] alternative has a 7-bitADCand 4 gain ranges; it also has time-stamping. The "All-in-One" front-end is based on the Front-end for Atlas TilecAL Integrated Circuit (IC) (FATALIC)[42] ASIC, and makes use of the current-conveyor concept. A radiation-hard ADCis incorporated into theFATALICchip, which uses 3 12-bit gain ranges.
Figure 33.(left)QIEsignal flow. (right)FATALICbasic circuit.
The new read-out scheme using high bandwidth links places much higher demands on the TilePPR than in the current system. The signal flow of the TilePPR is shown in Fig. 34. The TilePPR is responsible for receiving and routing data received from the drawers, sending trigger tower signals to the trigger, receiving and transmitting slow controls to the drawer, and establishing the system (currently TTC) timing to synchronise the readout stream with the DAQ. This system uses Virtex-7 and Kintex-7FPGAsandQSFPoptical transceivers.
High voltage supply and monitoring of the Photomultiplier tubes is also done in the mini-drawers. Currently two alternative systems are under study. In one case, HVfrom a singleHVfeed to the mini-drawer is adjusted for each PMT by a controller card similar to those on the current system. This card communicates with slow controls via the DB. The alternate system under study has the HVdistribution off-detector, with 12HVcables running to each mini-drawer.