Design Requirements
The expected instantaneous and total luminosities at the HL-LHC and the new
ATLAS
trigger scheme correspond to operation conditions which are beyond the design specifications of the read- out electronics of theATLAS
Liquid Argon(LAr) calorimeter system.In the currentLArreadout system [15,16], the detector signals are stored every 25 ns in analog pipelines on the FEBswhich are installed on the detector in a radiation environment. Upon arrival of aL1 trigger accept signal, four samples are digitized for each channel at the bunch-crossing of interest and are sent via optical links to the back-end system. The depth of the analog pipelines, the speed of the optical transmission, and the processing power of the back-end electronics do not allow to go beyond trigger accept rates of 100 kHz. Therefore, the current electronics is incompatible with the futureL0andL1trigger rates of 1 MHz and 400 kHz and latencies of10µsand60µs, respectively. Within the Phase-I Upgrade in the LHCLS2 shutdown, theLAr trigger readout will already be equipped with additional electronics to provide finer granularity signals to the currentL1calorimeter trigger system [17]. This signal path will stay and is designed to serve as L0 trigger input in the HL-LHCphase. TheL0trigger in theHL-LHCphase will be based on calorimeter and muon spec- trometer signals and will correspond to today’sL1trigger. The futureL1trigger will include also input from theITk.
Moreover, the current front-end electronics has been qualified [18] for total radiation doses which correspond to a total luminosity of1000fb−1, including safety factors accounting for uncertainties of the radiation background simulation and of the ASIC and Commercial Off-The-Shelf component (COTS)production processes. The luminosity to be collected duringHL-LHCoperation is therefore beyond the specifications of the current front-end electronics [19]. Exceptions are theLAr Trigger Digitizer Board (LTDB) that will be installed already during the Phase-I Upgrade [17] and the pre- amplifier systems of the HEC[20], which are installed inside the LArend-cap cryostat. The LTDB components and theHECpre-amplifier systems are designed to withstandHL-LHCequivalent radi- ation doses which is confirmed by dedicated irradiation studies [17,21].
The future trigger and radiation tolerance requirements thus imply a full replacement of the cur- rent front-end and back-end readout system, with the exception of the Phase-I trigger readout com- ponents and theHECpre-amplifier systems. The radiation tolerance requirements are summarized in Tab.14based on the current
ATLAS
detector geometry [19], and applying updated safety factors for the simulation of background levels. These have been measured and were found to be in good agreement with simulations [22]. The expected radiation levels will need to be further updated oncethe
ATLAS
detector options for theHL-LHCrunning are chosen.V.2.2
Readout Architecture Studies and R&D for
HL-LHC
The LAr readout electronics to be installed for the HL-LHC phase will implement radiation toler- ant front-end electronics which performs the pre-amplification and shaping of the analog signals of all 183,000 LArdetector channels and an early analog-to-digital conversion without on-detector buffering of data. A high-bandwidth optical-link system will transfer the data at 200-400 Tb/s to a FPGA-based back-end system, where digital signal filtering, energy reconstruction, preparation of L1trigger inputs and long-latency data buffering are performed. The replacement of theLArreadout electronics will allow an optimisation of the analog and digital signal processing in order to improve the trigger and physics input during high-luminosity operation and to mitigate pile-up effects.
Table 14. Radiation tolerance criteria of the LAr electronics for operation atHL-LHC for a total luminosity of3000 fb−1, including safety factors for background estimation, given in brackets. ForCOTS, an additional safety factor of 4 is included in case of production in unknown multiple lots. Furthermore, the
ATLAS
policy specifies annealing tests that allow reducing the enhanced low dose rate safety-factor to 1, which currently is set to 1.5 forASICsand 5 forCOTS.TID[kGy] NIEL[neq/cm2] SEE[h/cm2]
ASIC 0.75 (2.25) 2.0×1013 (2) 3.8×1012 (2)
COTS(multiple lots) 9.9 (30) 8.2×1013 (8) 1.5×1013 (8)
COTS(single-lot) 2.5 (7.5) 2.0×1013 (2) 3.8×1012 (2)
LVPS(EMBandEMEC) 0.58 (30) 9.2×1012 (8) 2.4×1012 (8)
LVPS(HEC) 0.17 (2.25) 4.7×1012 (2) 2.7×1011 (2)
The layout of the new LAr readout is sketched in Fig. 20. The future FEB-2 will amplify the detector signal, apply an analog shaping, digitize the signals with 40-80 MHz sampling frequency, serialize the data stream and send it out via fast optical links. The data from all 183,000LArchannels are received by the back-end Pre-Processor system, where digital filters are applied for optimized energy calibration and pile-up suppression. Input signals for the
ATLAS
L1 trigger are produced compatible with a 1 MHzL0trigger rate and a60µstotal latency requirement. AtL1accept, all data are sent to theATLAS
DAQsystem. TheDAQandL1trigger interface is foreseen to be theFELIX system (see SectionIII.5.1).TheFEB-2 boards will furthermore produce input signals to the LTDBs, which will have been installed on the detector during theLHCLS2 shutdown. These provide so-called Super-Cell trans- verse energy sums which are input to theL0trigger in theHL-LHCphase. TheL0data are received in the USA15 counting room by the LAr Digital Processing Boards (LDPBs), also installed in LS2. The LDPBscalculate calibrated transverse energies for each Super-Cell and provide their correct bunch-crossing assignment at a rate of 40 MHz. The total latency of less than1.2µsand the size of the off-detector data buffers are well within the requirements for theL0trigger system.
The Phase-I trigger readout system contains several custom components that can be consid- ered as evolutionary steps towards the Phase-II readout. The front-end LTDBis equipped with ra- diation tolerantAnalog-to-Digital Converters (ADCs), serializers and optical links, while theLDPBis based on high-performanceFPGAswith large data bandwidth (Altera Arria-10). A comparison of the achieved performance of the Phase-I system and the Phase-II requirements is shown in Tab.15. For all Phase-I components the R&D is in the final stages and close to be certified for series production. With the upgrade of theLArfront-end an optimisation of the readout system forHL-LHCcondi- tions will be possible. In particular, an improved treatment of in-time and out-of-time pile-up effects is expected with the future analog and digital signal processing. Extensive studies are on-going to evaluate different pulse shaping and digital signal filtering strategies based on a detailed simulation of the full readout chain for highest pile-up scenarios ofµ'200[23]. Figure21shows, as an exam- ple, the simulated response of a unipolar shaper designed in 180 nm technology and the effect of a unipolar shaping scheme on the signal baseline inADCcounts. A unipolar shaping would imply a reduction in power consumption compared to a bipolar shaping, and the preliminary simulation studies indicate that the baseline shift for the case of unipolar shaping is in the order of 100 ADC counts assuming a 12-bit ADC, even at highest pile-up of µ=200. If confirmed in more detailed studies, this would correspond to an increase in effective dynamic range that can be covered by the ADC.
In order to capture the expected range of deposited energies per LAr calorimeter cell, a dynamic range of 16-17 bits per channel is required. In the central LAr Calorimeter region the maximum input current per channel is about 10 mA and the noise should therefore not exceed 100 nA. Similar
Σ Optical Links Phase-II Upgrade Front-End Board Preampl. Layer Sum Boards [LSB] CLK Fanout Σ Σ Linear Mixer Shaper Ba se p la n e
Phase-II Upgrade Pre-Processor
FELIX Output OTx 80-100m fibers ADC ADC Optical Links ADC MUX/Serializer (FPGA) ADC
Digital Processing System (DPS)
Optical Receiver Deserializer Timing Trigger Control Rx FPGA L0 Trigger Processor Ped Sub Ped Sub Ped Sub Ped Sub E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR Σ 480Gbps/module 1.92 Tbps/board ~250 Gbps/board L1 Trigger Processor LAr Trigger Digitizer Board (LTDB)
Crate Monitoring Σ ADC & Gain Selec. MUX/Serializer FPGA L1-buffers Ped Sub Ped Sub Ped Sub Ped Sub E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR L0 Accept Logic & L1 Trigger Feature Extractor
Level-0,1 Calorimeter Trigger System L1 Accept Logic L0-pipelines ADC & Gain Selec. ADC & Gain Selec. ADC & Gain Selec. 2,3 Gains ORx Arrays OTx CLK Fanout ORx FELIX SDRAM TTC Partition Master
Figure 20. Architecture of the Phase-II readout system of the
ATLAS
LArCalorimeters. The new Phase-II readout components are shown along the top row of the signal flow. TheFEB-2boards are amplifying and shaping the detector signals and digitize all data at 40-80 MHz. High-bandwidth optical data-transmission is used to send the data to the back-end system equipped with Pre-Processor boards, which are the interface to the L1trigger and theATLAS
DAQ. The Super-Cell trigger readout, to be installed already during the Phase-I upgrade, is shown in the bottom half of the flow diagram. It will provide the input to the low-latencyL0trigger.
performance requirements hold for the otherLArCalorimeter areas. Cooling capabilities require the power per channel to be less than 50 mW. Furthermore, the serializer and optical transmitter should provide a data rate of at least 9 Gb/s per fibre excluding packaging and forward error corrections.
CustomASICsin technologies with feature sizes between 65 nm and 180 nm are being devel- oped to fulfill these requirements [24–26]. Pictures of prototype ADCchips developed within the Phase-I and Phase-II R&D processes are shown in Fig. 22, together with irradiation test results for one of the prototypes. All 12-bit ADCprototypes are confirmed to meet the Phase-II require- ments in terms of radiation and power consumption. Commercial 12-bit ADCswere tested within the Phase-I R&D and found to fulfill the specifications [17]. Recent custom developments include triple-redundant layouts and an active correction ofSingle Event Effect (SEE)effects [24], schemat- ically shown in Fig.23, which further improves radiation robustness.
The goal of the furtherASICdevelopment is an integration of the pre-amplifier, shaper andADC stages in a single chip in order to reduce the system complexity and power consumption. It also allows fewer supply voltages compared to the current system which will simplify the power distribu- tion system. Early successful designs of pre-amplifier and shaper in SiGe BiCMOS technologies
Table 15.Comparison of parameters of the Phase-I trigger readout system, which is entering series produc- tion in 2016, with the Phase-II Pre-Processor System of the
ATLAS
LArCalorimeters.Phase-I Phase-II
LArTrigger Readout LArPre-Processor System
Number of channels 34,000 183,000
ADCbit precision 12 10-14
ADCsampling frequency 40 MHz 40-80 MHz
Optical-link speed 5.44 Gb/s 10 Gb/s
Total front-end rate 25.2 Tb/s 200-400 Tb/s
Data rate toL1trigger 41.1 Tb/s (at 40 MHz) 20 Tb/s (at 1 MHz) Data rate
ATLAS
DAQ(at 0.1-0.4 MHz) 100 Gb/s 7 Tb/sNumber of I/O fibres perFPGA 66 120
Input rate perFPGA 205 Gb/s 1200 Gb/s
Output rate perFPGA 270 Gb/s 75 Gb/s
Figure 21. Left: Simulated pulse of a unipolar shaper in 180 nm technology. Right: Baseline shift in ADC
counts due to signal pile-up determined for a mean number of events perLHCbunch-crossing,µ, between 50 and 200 for different pseudo-rapidity ranges in the middle layer of theLArCalorimeters.
(IBM 8WL and IHP) achieved non-linearity and noise levels within the LArrequirements. Current design activities include 130-180 nmBiCMOS and 65 nmCMOStechnologies with successful im- plementations of the pre-amplification and unipolar and bi-polar shaping stages for 14-bit and 10-bit signal range, respectively. In both technologies pipelined SAR ADCs up to 12 bit precision have been prototyped, and developments towards a 14-bitADCin 65 nm technology are ongoing.
Since the dynamic range of the system extends to more than 16 bits, a single gain stage is not sufficient assuming the current radiation tolerantADCdevelopments. Design layouts and simulations are being performed, for example, for 2-gain systems with two 14-bitADCs, which may also ease the detector calibration procedure compared to the current 3-gain readout. In order to avoid a gain selection at the radiation tolerant front-end, the output of allADCsis foreseen to be sent to the back- end system, where the optimal gain selection can be applied digitally. This readout configuration, with two 14-bit ADCs per channel, is assumed as a baseline for the cost estimates of the LAr Calorimeter readout system (see SectionV.2.5).
Each of the 1524FEB-2 boards will send the data from up to 128 readout channels on about 16 fibre links with 9 Gb/s link speed, excluding data packaging and forward error correction. This
Figure 22.Left: Photographs of example test chips of a four-channel 12-bit 130 nmSAR ADC(top left) [26], of a four-channel 12-bit mixedSAR-pipeline 130 nmADC(top right) [25], and a 2-stage 65 nm 12-bit SARADC
(bottom) [24]. Right: SNDRmeasured for the prototype of a 65 nm 2-stage 12-bitSAR ADCafter irradiation up to 1 kGy [24]. Similar results are obtained for the other 12-bitADCprototypes [25,26].
will allow a transmission of 2×14bits per channel and bunch-crossing. Within the LArcommunity, aVCSEL array driver and transceiver module has been developed in 250 nm Silicon-on-Sapphire (SoS) technology and achieves 8 Gb/s [27], as demonstrated for a prototype in Fig.24. For going beyond this link speed, a technology with smaller feature size is however necessary. The data transmission targets of the CERN-wide optical-link projects,Low Power GBT transmitter (lpGBT)[28] and Versatile Link PLUS (VL+) [14], are planned to meet the LAr rate requirements and will be designed in 65 nm technology. In both projects, theLArdevelopment groups are closely involved. In case all front-end functionalities are laid out in the small 65 nm feature size, a further integration of all components into a completeFESOCis considered, as shown in Fig.23. R&D work for such an option is on-going and it has interesting advantages: no I/O between the shaper andADCreduces noise from parasitics, and no I/O between theADCand serializer will substantially reduce theADC power consumption.
An overall optimisation of the whole system is thus required, and is the subject of the current R&D of the
ATLAS
LArcommunity in order to select the optimal front-end solution, taking performance, feasibility and costs into account.TTC signals furthermore need to be sent to each of the 1524 FEB-2 boards in the front-end crates. These signals are planned to be directly transmitted on fibre links using theFELIXinfrastruc- ture and to be decoded by thelpGBT chipset. This avoids the use of a dedicated controller board as a single point of failure and makes the design of a dedicated control ASIC unnecessary. The number of clock and control fibres perFEB-2board will be at least 2, for redundancy, and at most 8, depending on the readout segmentation and the readout fibre mapping to the back-end system.
Feb. 5, 2015 11 A B in SEE Detector SEE Detector A B
• 3-dB SNR gain under normal condition (no SEE)
• If ∆Dout is large, chose the output of the ADC that is not hit
• Split-ADC also enables digital background calibration [3] Patent pending
2015 JINST 10 C04035
Figure 1. The block diagram of the potential phase-II FEB upgrade. The ADC continuously digitizes the
analog output of the shaper without analog buffering.
1.1 SAR versus pipeline
There are two principal ADC architecture choices for high-energy physics (HEP) applications. One is the SAR ADC and the other is the pipelined ADC. Both can operate at medium-to-high resolutions, while the pipeline usually displays a higher throughput than the SAR.
One challenge of implementing a pipelined ADC in scaled CMOS is that the low supply volt- age in these processes makes the design of the high-gain, high-speed residue amplifier (RA) — necessary for inter-stage residue voltage transfer — difficult, thus degrading the linearity and noise performance of the ADC, which usually translate into high power consumption, large die size, and high cost.
In contrast, due to the series conversion process, a SAR ADC is much more power and area efficient — it only contains three main components, a switched-capacitor (SC) digital-to-analog converter (DAC), a zero-crossing comparator, and some SAR logic and registers, leaving ample room for redundancy circuits to be implemented for radiation tolerance. We will show in section II that with technology advancement, CMOS SAR ADCs now meet the conversion speed require- ment for ATLAS LAr application. The characteristics of advanced CMOS technologies (e.g., a 40-nm or 65-nm process) under irradiation, showing significant decrease of the radiation-induced charge trapped in the oxide and interface states [15], also greatly benefit the TID tolerance of the circuits. The improved conversion speed, combined with the prominent advantage in power and area consumptions, makes the CMOS SAR a suitable and perhaps preferred candidate for future HEP applications. In section III, a 12-bit, 45-MS/s SAR ADC prototype is presented. An offset double conversion (ODC) technique will be introduced for the calibration of the DAC bit weights. In section IV, a 12-bit, 160-MS/s two-step SAR ADC prototype with opportunistic PN injection calibration is showcased, followed by the TID testing results of this prototype in section V. Lastly, a short conclusion is given in section VI.
2 Recent advancement of SAR ADC
In the last decade, great progress has been made in SC SAR ADCs for mainstream commer- cial applications requiring 12–14 bits and 50–200 MS/s speed [16–18]. Particularly, the appli- cation of built-in redundancy and digital calibration to a large extent has helped lift many critical
– 2 –
Figure 23. Left: Concept of split ADCs with SEE detection mechanism, which selects the ADCwhich is not hit by an ionising particle in case a difference between the twoADCoutputs is observed [24]. Right: A
FESOCwill integrate the analog pre-amplification, shaping, the analog-to-digital conversion and the serializer and optical-link components in a singleASIC.
Figure 24.Left: Image of a prototype VCSEL array driver in 250 nm SoS technology for data transmission up to 8 Gb/s [27]. Right: Eye diagram taken with a prototype of the VCSEL array driver transmitting a pseudo-