Marketing verde

Building on our experimental results of chapter 7, we choose a heterostructure with the same active layer system as sample 𝐺1_{on which we fabricate triple-gated QPCs. Thereby,}

we employ the refined processing recipe for device fabrication with which we were able to achieve a robust and reproducible gating response of the 2DEG in top-gated Hall bar measurements. These newly fabricated TrG devices present an auspicious testing platform to accomplish electric stability of our QPCs under gate operation.

All experiments in this chapter are conducted at 𝑇 = 1.5𝐾 in the non-illuminated state since we determined that illumination generally increases uncontrollable charge redistribution processes in our devices. The samples are cooled down to cryogenic temperatures with the ohmic contacts set to the laboratory ground potential and the finger-gate electrodes, i.e. the SG-electrodes and the CG-electrode, fixed at 𝑉𝑆𝐺 = 𝑉𝐶 𝐺 = 0𝑉. Some of

the samples are furthermore equipped with a global TG with which we are able to control the electron density of the 2DEG. For these samples we apply a TG-voltage of 𝑉𝑇 𝐺 =0𝑉 during cool-down. Unless otherwise specified, the TG-voltage is held constant

at 𝑉𝑇 𝐺 =0𝑉 during a 1D conductance measurement. For most measurements a sweep

rate of 5 − 10𝑚𝑉/𝑠 is applied.

8.1.1 Reproducibility

Figure 8.1(a) shows five subsequent conductance curves of a triple-gated QPC. The conductance 𝐺 is plotted as a function of the symmetrically applied SG-voltage 𝑉𝑆𝐺

in multiples of 2𝑒2_{/ℎ, whereby the CG-voltage is held constant at 𝑉}

𝐶 𝐺 = +0.3𝑉. No

serial channel resistance 𝑅𝑐 ℎ is subtracted. All conductance curves exhibit two clear SG-

voltage regimes, i.e. area (I) and (II), which are characteristic for finger-gate-defined 1D constrictions: In regime (I), the area underneath the SG-electrodes is depleted, in regime (II) the 1D channel is laterally pinched off wherein quantized conductance features arise. The presence of only two regimes in the total conductance curve here presents a significant difference in the transport characteristics of the QPC under gate operation as compared to the triple-gated devices, which we analysed in the preceding 1D transport study in chapter 6. Therein, TrG-defined QPCs all exhibited a third gating area in-between the here observed areas (I) and (II). We assigned the emergence of this third gating regime to a charge accumulation underneath the positively biased CG-electrode: Negative charge carriers, that were fixed at parasitic trap states at the semiconductor/dielectric interface underneath the CG, had to be removed in these samples, whereby a more negative SG-voltage was required as compared to solely SG-defined QPCs. The lack of this third depletion regime for the newly fabricated QPC device demonstrates that we have effectively and efficiently removed detrimental defect sites from the semiconductor/dielectric interface in

1_{Sample 𝐺 from wafer C160420B (studied in subsection 7.2.2): 20𝑛𝑚 InGaAs QW with 130𝑛𝑚 InAlAs}

8.1 Realization of robust ballistic 1D conductance

Figure 8.1:Conductance measurements at 𝑇 = 1.5𝐾 in the non-illuminated

state with no 𝑅𝑐 ℎ subtracted, 𝑉𝐶 𝐷 = 0𝑉. (a) Sample C160420B3 TrG1 with

𝑉_{𝐶 𝐺} = +0.3𝑉: Five subsequent conductance measurements with characteristic gating areas (I) and (II). Odd numbers depict the depletion curves of the QPC, even numbers mark the corresponding up-sweeps of 𝑉𝑆𝐺. The inset presents a

zoom into the area near pinch-off. (b) Sample C160420B2 TrG1 with 𝑉𝐶 𝐺 =0:

Four subsequent depletion curves (chronologically numbered), being thermally recycled after each measurement with 𝑉𝐶 𝐷 =0𝑉.

the heterostructure. Furthermore, a significant achievement presents the elimination of the formerly present hysteresis between the down-swept conductance measurements (odd numbered curves) and the subsequent up-sweep measurements (even numbered curves). The inset in figure 8.1(a) presents a zoom into the conductance area near pinch-off. Three clear steps in 𝐺 can be identified, the lowest step being most pronounced. We want to note that the conductance steps do not match integer multiples of 2𝑒2_{/ℎsince no channel}

resistance is subtracted here. We find that the conductance curves of all SG-sweeps are fully congruent. This clearly shows that we gained electric stability in our samples by means of the ameliorated device fabrication method.

Figure 8.1(b) displays four depletion curves between which the device is warmed up to RT and then cooled down again with 𝑉𝐶 𝐷 =0𝑉. We find that all curves except measurement

(1), which is slightly shifted into the negative 𝑉𝑆𝐺-direction as compared to measurements

(2) to (4), are fully congruent. Generally, we obtain a good reproducibility of the 1D transport properties in successive biased cool-downs for all of our newly fabricated devices. This proves that we can efficiently preset the electronic configuration inside the heterostructure. Furthermore, we find that the height of the individual conductance steps after each cool-down is also well reproducible, meaning that the transmission coefficient of a particular 1D mode is identical after each cool-down, which further confirms that we have created the same electric potential environment in the QPC.

Accordingly, we are able to demonstrate reproducible and non-hysteretic 1D conductance in our TrG-defined QPC devices by means of the refined device fabrication process. A second key element towards the realization of robust, ballistic 1D transport in a QPC

8 Ballistic conductance in InGaAs/InAlAs-based systems

device is the attainment of reliable persistence of the conductance over time. This will be analysed in the following.

8.1.2 Time stability

Figure 8.2:Time stability of the conductance through TrG devices at 𝑇 = 1.5𝐾

in the non-illuminated state with no 𝑅𝑐 ℎ subtracted and 𝑉𝐶 𝐷 = 0𝑉. (a) - (c)

Sample C160420B2 TrG1 with 𝑉𝐶 𝐺 = +0.05𝑉: (a) 𝐺 as function of 𝑉𝑆𝐺, colored

dots mark the measurement points, at which the persistence of 𝐺 over time 𝑡 is tested. (b) 𝑉𝑆𝐺 over time 𝑡. (c) 𝐺 as a function of time 𝑡. (d) - (e) Sample

C160420A1 TrG1 with 𝑉𝐶 𝐺 = +0.1𝑉: (d) 𝐺 as function of 𝑉𝑆𝐺, the colored dot

marks the measuring point. (e) 𝐺 as a function of time 𝑡.

Figure 8.2(a) displays a section of the conductance curve near depletion of a triple-gated QPC (same as in figure 8.1(b)). The colored dots mark the positions along the conductance curve at which we test the time stability of the conductance through the QPC. For this experiment, we choose the first three conductance steps as measuring points. At these points, we keep 𝑉𝑆𝐺 fixed for a dwell time of 30 minutes before we sweep 𝑉𝑆𝐺 to the next

testing point. Figure 8.2(b) displays the applied 𝑉𝑆𝐺 as a function of time 𝑡. The obtained

conductance 𝐺 over time 𝑡 is shown in figure 8.2(c). We find 𝐺 to be remarkably stable over the whole dwell time. This indicates that charge redistribution in the vicinity of the 1D channel is efficiently suppressed when the Fermi level lies in-between two subsequent 1D subbands. The noise on the signal slightly increases with increasing G, implying an increase of charge fluctuations as the width of the channel increases and the subband distance reduces.

Figure 8.2(d) and (e) show the time stability measurement of an InAlAs-terminated QPC device, with an additional InAs inset in the InGaAs QW. The corresponding heterostructure is sketched in figure 8.6. For this device, we adjust the measuring points right before the onset of the first conductance step (see figure 8.2(d)). The flank of a conductance step presents the most sensitive measuring point on the transport curve. Here, a dwell time of 70 minutes is applied. The time stability of the conductance is shown in figure 8.2(e). We find 𝐺 to be reasonably stable during the whole dwell time. There is only a slight increase of 𝐺, which occurs rather stepwise. We attribute this behavior to small