Capítulo 3. Nuevas formas de consumo
3.2. Adaptación de las marcas
3.2.1. Responsabilidad Social Empresarial
As described at the beginning of chapter 5, the electron-providing InAlAs deep level donor states are assigned to As-related antisite defects in the InAlAs barrier layers. In order to reduce the background Coulombic disorder potential in the system, we aim to decrease the density of these MBE growth-related defect states. Thus, we follow an experimental approach by Campion et al. [195], who reported a significant reduction of As-related antisite defects by employing As2instead of As4 at low substrate temperatures for the
epitaxial growth process of their GaMnAs layer films. Equivalently to a MBE growth study of Chen et al. [38], we transfer these modified growth parameters from Campion et al. [195] to the epitaxy of our In0.75Ga0.25As/ In0.75Al0.25As layer systems. By supplying
As2 instead of As4as group-V material during the MBE growth process, we fabricate
two new wafer structures. The BEP of As2 is kept at 8 · 10−6𝑇 𝑜𝑟 𝑟. We furthermore modify the substrate temperature 𝑇𝑎 𝑐𝑡 of the active layer to stress the influence of 𝑇𝑎 𝑐𝑡
on the InAlAs defect state formation: For wafer C170731A, we choose 𝑇𝑎 𝑐𝑡 = 430 ◦
𝐶, being similar to 𝑇𝑎 𝑐𝑡 of our previously analysed heterostructures during the course of
this thesis. For wafer C170731B, we apply a reduced temperature of 𝑇𝑎 𝑐𝑡 =330 ◦
𝐶. For better comparison with literature, we monitor and control the substrate temperature via a BandiT system in addition to the standardly used optical pyrometer.
wafer n𝒗 𝒅𝑷𝒅𝒂𝒓 𝒌(·1011cm−2) 𝝁𝒗 𝒅𝑷𝒅𝒂𝒓 𝒌(cm2/Vs) n𝒊𝒍 𝒍𝒗 𝒅𝑷(·1011cm−2) 𝝁𝒊𝒍 𝒍𝒗 𝒅𝑷(cm2/Vs)
C170731A / / 3.0 3000
C170731B / / 2.1 3000
Table 7.3:Transport properties determined via vdP measurements at 𝑇 = 4.2𝐾.
Figure 7.18:VdP Hall measurements of wafer (a) C170731A (b) C170731B in
the illuminated state at 𝑇 = 1.5𝐾.
Figure 7.18 depicts a sketch of the newly grown heterostructure of wafers C170731A and C170731B. Since we expect the intrinsic doping density to be reduced by means of the adjusted growth-parameters, we introduce a 15𝑛𝑚 Si modulation doping layer
7.7 Conclusion
above the QW, whereby dopant segregation into the InGaAs QW is circumvented. The introduced Si doping density is 𝑛𝑑𝑜 𝑝 ≈2 · 1011𝑐𝑚
−2. For rapid transport characterisation,
we fabricate vdP samples. The corresponding Hall measurements in the illuminated state are shown figure 7.18(a) and (b). The determined electric transport properties are listed in table 7.3. As indicated by the backslash in the table 7.3, we are not able to drive a current through the vdP samples of both wafers in the non-illuminated state. Only after illumination, the samples become conducting, yet, we determine an exceptionally low mobility of only 𝜇𝑖𝑙 𝑙
𝑣 𝑑𝑃 =3000𝑐𝑚
2/𝑉 𝑠for both samples. Remarkably, however, for sample
C170731A the determined electron density 𝑛𝑖𝑙 𝑙
𝑣 𝑑𝑃 after illumination is only slightly higher
than the introduced Si modulation doping density 𝑛𝑑𝑜 𝑝, for sample C170731B we even
find 𝑛𝑖𝑙 𝑙
𝑣 𝑑𝑃to perfectly match 𝑛𝑑𝑜 𝑝. This is a clear indication of a tremendous reduction of
the As-related antisite defects inside the heterostructure via utilisation of As2instead of
As4.
Figure 7.19: (a)20 𝑥 20𝜇𝑚 plan view AFM image of wafer C170731A (b) 3D
plot of profile of wafer C170731A (c) 20 𝑥 20𝜇𝑚 plan view AFM image of wafer C170731B (d) 3D plot of profile of wafer C170731B.
To comment on the tremendous mobility reduction in these heterostructures, we analyse the wafer surface via AFM as displayed in figure 7.19. Wafer C170731A with 𝑇𝑎 𝑐𝑡 =430
◦
𝐶 exhibits a rough morphology in form of 3D islands instead of the typical cross hatching pattern, whereas wafer C170731B with 𝑇𝑎 𝑐𝑡 =330
◦
𝐶shows a very close meshed cross hatching surface texture. The transition from 2D layer-by-layer growth to 3D island formation is ascribed to elastic strain relaxation at the edges of the formed islands, whereby the crystal energy is minimized. A lowering of the substrate temperature, as in the case for wafer C170731B, extends the 2D layer-by-layer growth regime since the surface diffusion length of our growth material atoms is reduced, preventing the system from reaching thermal equilibrium [38, 109, 196]. Accordingly, we assign the reduced mobility to altered growth kinematics with As2as compared to As4.
Nevertheless, this experiment clearly shows an enormous reduction of InAlAs deep level donor states by applying As2as group-V material together with an additionally lowered
substrate temperature 𝑇𝑎 𝑐𝑡 during the active layer growth.
7.7 Conclusion
In this chapter, we evaluated the response of In0.75Ga0.25As/ In0.75Al0.25As heterostructures
7 Gating response of various III-V heterostructures
from intrinsic charge reconfigurations. In order to gain a better understanding of the electrostatic response of the system, we conducted a series of measurements on top-gated Hall bar samples, in which we focused on the aspect of surface termination of the semiconductor layer system in particular.
For gate stackings, as the ones used in chapter 6 for our QPC devices, we find a parasitic conductive layer already to be present at the interface of the 5𝑛𝑚 InGaAs capping layer and the Al2O3dielectric for a TG-voltage of 𝑉𝑇 𝐺 =0𝑉. To restore capacitive coupling to
the 2DEG, this interface layer has to be depleted via the application of a negative TG- voltage. Furthermore, biased cool-down measurements on this heterostructure revealed the presence of additional parasitic energy states above the InGaAs /Al2O3interface. We
expect these defect states to be located inside the dielectric layer in the form of deep trap states. A reduction of the InGaAs cap thickness to 2.5𝑛𝑚 in combination with a chemical removal of residual native oxides leads to a significant enlargement of the accessible and non-hysteretic density range in the heterostructure. For 𝑛𝑠 & 7 · 1011𝑐𝑚
−2charge
migration from the QW towards the interface still sets in, which manifests itself in form of a two-stage charge transfer process, described in detail in our phenomenological charge transfer model. We infer that the InAlAs deep level donor states inside the spacer layer, as well as the interface density of states play a key role in the process of charge migration. A high interface density of states, which can be effectively populated with free electrons from the InAlAs deep level donor states, leads to the formation of a trough-shaped InAlAs spacer band profile. During charge migration, electrons become effectively localized in this potential dip, such that a metastable state inside the system is generated. This process is characterised by a robustly adjustable decrease of the charge density inside the QW when 𝑉𝑇 𝐺 is further increased, whereby capacitive coupling to the QW is still maintained.
For increasing positive TG-voltages, electrons are then transferred to the interface and a parasitic conductive layer is created.
In an attempt to reduce the interface states of the heterostructure, we remove the low band gap InGaAs capping by wet-chemical etching, whereby we create an InAlAs surface termination. For these samples, the charge transfer rate from the QW towards the interface during gating is effectively reduced as compared to InGaAs-terminated samples. Yet, the maximum achievable electron density, marking the end of the linear gating regime according to the field-effect, of InAlAs-terminated samples is equivalent in magnitude as for the InGaAs case. Increased interface roughness due to the etching process increases the probability of gate leakage in these InAlAs devices. This problem may be circumvented for samples with MBE-grown InAlAs surface terminations.
We tested the possibility to reduce the defect density inside our gate stacking via rapid thermal annealing in a forming gas atmosphere. For InGaAs-capped samples, we determined no significant modification of the gating response after annealing. For InAlAs-terminated samples, however, we found clear indications for a substantial material intermixing at the interface.
In addition, we examined alternative dielectric materials, MBE-grown MgO and HfO2
in combination to Al2O3, in our samples. These devices exhibited a similar gating
7.7 Conclusion
found indications for an increased density of interface states. We want to point out to the fact that all of our tested dielectrics contain oxygen, presumably leading to the creation of oxygen-metal-bonds at the interface. Non-oxide based dielectrics present themselves as interesting alternatives for further tests.
By means of analysing the electron mobility in regard to the corresponding charge density, we were able to identify the dominating scattering mechanism in the heterostructure to be formed by scattering on 3D charged impurity sites. Charge migration towards the interface introduces a remote 2D Coulombic disorder potential, which then effectively contributes to the scattering in the 2DEG.
On the basis of the analysis in this chapter, we understand the determined 1D conduction properties of our QPCs in chapter 6: The negative applied SG-voltage lifts the charged interface states of the 5𝑛𝑚 InGaAs-capped samples above the Fermi level. This imbalance leads to charge transfer from electrons underneath the SG-electrodes towards surrounding energy states at the interface. In our 1D transport measurements, this charge migration then manifests itself in form of a hysteresis between the depletion and the opening of the QPC, as well as in the experimentally observed time instability of the 1D conductance near depletion. This behavior should be efficiently reduced by the elimination of interface states in form of a reduced InGaAs cap thickness in combination with wet-chemical oxide removal, or, alternatively, with InAlAs-terminated samples. We expect an equivalent 1D transport behavior for both types of interface terminations.
As comprehended in our charge transfer model, we ascribe both, the limitation of the linear gating area following the classical field-effect, as well as the hampered ballistic transport in our finger-gate-defined 1D constrictions, to the InAlAs deep level donor sites. Their effect in 2D measurements is well described in subsection 7.2.3; in 1D, the Coulombic disorder potential leads to the generation of localized states in the QPC channel and to less well-defined conduction steps due to enhanced energy broadening and conductance oscillations at low temperatures.
By modifying the MBE growth parameters, we were able to tremendously reduce the As-related antisite InAlAs defect states. We currently optimize the epitaxy process of (InAs/) InxGa1-xAs/ InxAl1-xAs in the framework of a doctoral thesis with a view to
mobility enhancement and the controllability of SOI [126].
In the next chapter, new QPC devices are fabricated on InAlAs-terminated heterostructures, as well as on structures with a thin InGaAs capping layer, to test the effect of the reduced parasitic interface density of states in our QPC measurements. Since we found the reproducibility of the 2D transport characteristics for InGaAs-capped samples to be increased as compared to their InAlAs counterparts, we start the 1D transport measurements with QPC samples of wafer C160420B, being equipped with a 2.5𝑛𝑚 InGaAs capping layer. Thereby, the risk of gate leakage for InAlAs-terminated samples due to surface roughness is circumvented.
Ballistic conductance in
InGaAs/InAlAs-based systems
8
In chapter 6, in which we thoroughly tested the 1D transport characteristics of our finger-gate defined QPCs in highly mobile In0.75Ga0.25As/ In0.75Al0.25As heterostructures,
we found the ballisticity and electric stability of the devices severely deteriorated: A hysteresis between the depletion and the opening of the QPCs develops, which scales in magnitude with the dwell time in or near pinch-off, as well as with the chosen 𝑉𝑓 𝑖𝑛𝑎𝑙
𝑆𝐺 ,
i.e. the minimum SG-voltage applied in pinch-off. Thus, no stable working point on the conductance curve in the pinch-off area could be adjusted. In addition, ballistic conductance was significantly diminished when the QPCs were reopened after pinch-off. In a charge transfer model, which we developed in chapter 7, the electric instabilities of the 1D devices were discussed and unveiled: Parasitic energy states at the InGaAs/Al2O3
interface, together with deep level donor states inside the InAlAs spacer layer are responsible for the observed adverse charge reconfigurations inside the layer system under gate operation. By means of a complete removal, respectively a sufficient reduction of the InGaAs cap thickness, combined with a chemical elimination of residual III-V-based oxides at the semiconductor surface, we could demonstrate electric stability of our gate stacking over a wide bias (and thus electron density) range in MT measurements on top-gated Hall bar devices.
In this chapter, our newly gained insight into the (InAs/)In0.75Ga0.25As/ In0.75Al0.25As-
based material system allows us to implement another step towards the realization of reliable 1D transport in these heterostructures.
8 Ballistic conductance in InGaAs/InAlAs-based systems