Tendencias sustentables: slow vs. fast

Figure 8.4:Conductance curves of sample C160420B3 TrG1 at 𝑇 = 1.5𝐾 in

non-illuminated state, 𝑉𝐶 𝐷 = 0𝑉. (a) 𝐺 as function of 𝑉𝑆𝐺 for various 𝑉𝐶 𝐺,

increased in 0.1𝑉-steps with an offset bias of |Δ𝑉 | = 1𝑉 applied between the two SG-electrodes. (b) - (d): Comparison of symmetric (light grey curves), i.e. |Δ𝑉 | = 0𝑉, and asymmetric (dark grey curves), i.e. |Δ𝑉 | = 1𝑉, SG-sweeps for (b) 𝑉𝐶 𝐺 = +0.2𝑉 , (c) 𝑉𝐶 𝐺 = +0.6𝑉, (d) 𝑉𝐶 𝐺 = +0.8𝑉.

In a next step, we start to shift the QPCs laterally in space. This is done by asymmetrically biasing the two SG-electrodes: An offset voltage Δ𝑉 is applied between SG1 and SG2 so that 𝑉𝑆𝐺1 ≠ 𝑉𝑆𝐺2. The SG-electrodes are then parallely sweeped into negative

direction towards channel depletion. Due to the applied Δ𝑉, the QPC channel is laterally displaced in space as compared to the symmetrically biased case. Accordingly, the electric environment of the 1D constriction is altered since the respective impurity arrangement is different as the position of the QPC in the 2DEG changes [144]. By utilising this method, we are able to circumvent individual scattering centers, which act upon the QPC.

Figure 8.4(a) shows several depletion curves for different CG-voltages of the same device as analysed in the preceding subsection 8.2.1. Here, an offset voltage of |Δ𝑉 | = 1𝑉 is applied

8 Ballistic conductance in InGaAs/InAlAs-based systems

between SG1 and SG2. For clarity, solely one sweep-direction of 𝑉𝑆𝐺 is displayed since

the opening and depletion curves coincide. As for the symmetrically biased case, with increasing 𝑉𝐶 𝐺the conductance plateaus shift towards integer multiples of 2𝑒2/ℎ. The first

two conductance steps are much more pronounced than for the previous symmetric SG- sweeps with |Δ𝑉 | = 0𝑉, which have been shown in figure 8.3. This phenomenon is most pronounced in the second conductance step. Higher-order conductance steps, however, are hardly distinguishable. By means of three exemplary conductance measurements with different 𝑉𝐶 𝐺, we compare the conductance features of the asymmetrically and

the symmetrically biased transport measurements of QPC C160420B3 TrG1: Figure 8.4(b) displays the symmetrically biased conductance measurement together with the asymmetrically biased curve for a CG-voltage of 𝑉𝐶 𝐺 = +0.2𝑉, figure 8.4(c) shows the

two conductance curves for 𝑉𝐶 𝐺 = +0.6𝑉 and figure 8.4(d) displays the measurements at

𝑉𝐶 𝐺 = +0.8𝑉. These two sets of measurements are representative for the majority of the

conductance curves that we obtain with our devices. The horizontal offset between the two conductance curves is due to the offset voltage |Δ𝑉 | in the asymmetrically biased case. We find the height, as well as the width of the conductance steps of the two measurements to differ from each other for all three 𝑉𝐶 𝐺. This clearly demonstrates that we face unique

scattering situations in all of the six different potential configurations, which we adjust by 𝑉𝐶 𝐺 and |Δ𝑉 |. Consequently, we conclude that impurity disorder in the vicinity of the

QPCs strongly influences the 1D transport properties in the devices.

Figure 8.5:Conductance curves of sample C160420B2 TrG1 at 𝑇 = 1.5𝐾 in the

non-illuminated state with an offset bias of |Δ𝑉 | = 50𝑚𝑉. The inset displays a zoom into the area near depletion with 𝑅𝑐 ℎ =2.8𝑘Ω taken into account.

Figure 8.5 displays a particularly well-resolved conductance curve measured with one of the InGaAs/InAlAs QPCs. Hereby, a CG-voltage of 0𝑉 and an offset bias of |Δ𝑉 | = 50𝑚𝑉 are applied. Four very robust and well-defined plateaus are clearly visible. Subtracting a channel resistance of 𝑅𝑐 ℎ =2.8𝑘Ω matches the first two conductance steps well to 2𝑒2/ℎ

and 4𝑒2_{/ℎ. For higher-order steps, this value of 𝑅}

𝑐 ℎ does not result in even order of 𝐺. As

the effective width of the channel increases for those modes, the actual channel resistance decreases and thus deviates more and more from this value of 𝑅𝑐 ℎ.

8.3 1D conductance in alternative heterostructures

8.2.3 Conclusion

Generally, we are able to effectively tune the conductance in our TrG-defined QPC constrictions via the CG-electrode. Furthermore, the asymmetrical biasing of the SG- electrodes presents a further control knob for the ballisticity in the system. Thereby, a device-dependent optimum of ballistic conductance can be adjusted. For the application of the QPC as , e.g., a charge sensor in a qubit device, a fine-tuning of the conductance characteristics by moving the QPC in space is commonly used. For the all-electrical spin-FET device, however, this tuning knob is not well-suited: The device concept is based on two QPCs, which have to be perfectly aligned in the transport direction (see section 3.3). Consequently, a lateral shift of one QPC with respect to the other leads to enhanced backscattering, which would deteriorate the ballisticity and hence the spin signal. Thus, for more complex device applications, we suggest to improve the ballistic conductance in the heterostructure by eliminating the mobility-limiting scattering mechanisms which impair the ballisticity in the 1D channels. In our 2D transport study in chapter 7, we identified the InAlAs deep level donor states as the dominating scattering source in the material system. A reduction of the density of these defect states presents itself as pivotal for the realization of multi-component mesoscopic devices.

8.3 1D conductance in alternative

heterostructures

The spin-FET device, presented in section 3.3, consists of two serial QPCs, which exploit Rashba-type SOI in 1D constrictions whereby a highly spin-polarized current is created. The spin-polarization direction of the current is modulated by a middle-gate, which modifies the structural inversion asymmetry of the 2DEG via the applied gate electric field. Accordingly, more intricate InGaAs/InAlAs-based heterostructures are interesting substrate materials for this device application: An In0.75Ga0.25As QW with an

additional InAs inset offers a larger intrinsic SOI than a pure In0.75Ga0.25As QW [55]. In

addition, 2D electron systems, which are closer to the semiconductor surface - and thus to the QPC-defining finger-gate electrodes - would be beneficial in the above described device application, since the electric field of the gate electrodes is more well-defined as compared to heterostructures with a larger InAlAs barrier thickness. Thus, we conduct further experiments with alternative active layer systems in addition to the so far utilised heterostructure, which is composed of a 130𝑛𝑚 InAlAs spacer and a 20𝑛𝑚 InGaAs QW. Figure 8.6 displays a sketch of the gate stacking of a newly fabricated QPC device (sample C160420A1 TrG53_{). The QW is composed of 16𝑛𝑚 In}

0.75Ga0.25As with a 4𝑛𝑚 InAs

inset. This two-step QW is separated from the dielectric layer by an In0.75Al0.25As spacer

layer with a thickness of approximately 90𝑛𝑚.

8 Ballistic conductance in InGaAs/InAlAs-based systems

Figure 8.6: Sketch of

layer structure of sample C160420A.

Figure 8.7(a) shows the conductance through the TrG-defined constriction for various 𝑉𝐶 𝐺. The SG-electrodes are biased

symmetrically. For clarity, only depletion curves are plot- ted here, since we find the downwards- and upwards-swept curves to coincide. The conductance measurements show the expected gating response to an increase of 𝑉𝐶 𝐺: The

pinch-off point 𝑉𝑝 of the conductance shifts towards more

negative values of 𝑉𝑆𝐺. Furthermore, we find that the higher

𝑉_{𝐶 𝐺} is chosen, the better the quality of the conductance steps. For all applied 𝑉𝐶 𝐺, three to four conductance steps clearly

develop. In contrast to the samples discussed in the preceding sections, however, we find the quantization steps to be less uniform. The step height of the individual plateaus differ strongly, which indicates a particular mode-dependency of the transmission coefficients. Furthermore, some of the conductance steps, e.g., the first step of the measurements with 𝑉𝐶 𝐺 =0𝑉 and 𝑉𝐶 𝐺 =0.2𝑉, are hardly visible, yet re-emerge

for higher CG-voltages. These observations point towards an increase of the disorder potential inside the heterostructure, affecting the transport through the QPC. Since we have applied the same MBE growth conditions as for the previously studied samples, we attribute the enlarged potential disorder primarily to the etching process (which was employed in order to obtain the InAlAs surface termination) of the semiconductor surface. We suppose that this process generates additional interface roughness. The reduction of the InAlAs spacer thickness from 130𝑛𝑚 to 90𝑛𝑚 further enhances the impact of the interfacial disorder potential on the 1D channel. To support this hypothesis, investigating a greater number of samples is required to eliminate a misinterpretation based on the limited statistics.

Figure 8.7: Conductance curves at 𝑇 = 1.5𝐾 in non-illuminated state with

𝑅_{𝑐 ℎ} = 0𝑘Ω, 𝑉_{𝐶 𝐷} = 0𝑉 and |Δ𝑉 | = 0𝑉 (a) Sample C160420A1 TrG5 : 𝐺 as function of 𝑉𝑆𝐺 for various 𝑉𝐶 𝐺. (b) 𝐺 as function of 𝑉𝑆𝐺 of four different

samples: sample A: C160420B2 TrG1, sample B: C160420B3 TrG1, sample C: C160406B1 TrG1, sample D: C160420A1 TrG5.

8.3 1D conductance in alternative heterostructures

labeled as samples A to D, at a CG-voltage of 0𝑉. Samples A and B, which we already analysed in the previous sections in this chapter, stem from different positions of the same wafer, i.e. wafer C160420B. The newly analysed sample C is composed of a 2.5𝑛𝑚 In0.75Ga0.25As capping layer, a 35𝑛𝑚 In0.75Al0.25As spacer and a 20𝑛𝑚 In0.75Ga0.25As

QW. Thus, the distance between the QW and the semiconductor/dielectric interface is significantly smaller than for all other tested devices so far. Sample D is the above discussed QPC device C160420A1 (see figure 8.7(a)), whose conductance response is plotted here for comparison. All four samples exhibit the SG-characteristic depletion-form of the conductance curve. The 1D transport quality and behavior of sample A is equivalent to the conductance in sample B: Although the depletion curves are horizontally shifted with respect to each other, the conductance steps are well resolved in both measurements. Hence, we conclude that the 1D transport properties in different QPC devices, which are identical in composition, are well reproducible. Sample C, however, shows a quite different transport behavior: Even for 𝑉𝑆𝐺 =0𝑉, we determine a high channel resistance, whereby

the conductance is reduced to around 6𝑒2_{/ℎ (no serial resistance 𝑅}

𝑐 ℎ is subtracted).

Furthermore, we find the ballisticity in this device to be severely impaired since no clear conductance steps develop, even when we increase 𝑉𝐶 𝐺up to +2𝑉. Also a variation of 𝑉𝑇 𝐺

does not improve the ballistic conductance in this device. Adversely, a hysteresis develops for all applied 𝑉𝐶 𝐺-values as shown in figure B.4 in the appendix. We attribute this

hysteretic behavior to charge migration between defect states at the In0.75Ga0.25As/Al203

interface and the QW. Our experimental findings with sample C point to a markedly enhanced influence of potential disorder on the 1D transport in surface-near devices. Analysing the 2D gating response of this top-gated Hall bar sample while 𝑉𝑆𝐺 = 𝑉𝐶 𝐺 =0𝑉

is applied reveals a saturation of 𝑛𝑠 for 𝑉𝑇 𝐺 > 0𝑉. The corresponding MT measurement

sequence is shown in figure B.2 in the appendix. This early onset of the charge density saturation resembles our experimental findings in chapter 7 of sample 𝐴4_{and of samples}

𝐵 to 𝐷5. For these devices, we determined a large density of parasitic energy states inside the dielectric and at the semiconductor/dielectric interface. However, for sample C here, we employed the ameliorated device fabrication process, whereby the detrimental interfacial density of states is expected to be significantly reduced. We interpret the recurrence of the hysteretic gating response, as well as the formation of the parasitic conductive interface layer even at small 𝑉𝑇 𝐺to a charge transfer from the QW towards the

interface, mediated by the deep level InAlAs donor states owing to the reduced InAlAs spacer layer thickness of 35𝑛𝑚.

We summarize that the heterostructure/dielectric interface clearly affects the robustness of the QPCs in two ways: For etched heterostructure surfaces with a reduced spacer thickness, the disorder potential in the constriction is increased, whereby our ability to control the formation of conductance steps is limited. For surface-near samples a

4_{Sample 𝐴 (wafer C160429A): Hall bar sample of a deeply buried and undoped}

In0.75Ga0.25As/In0.75Al0.25As QW with 5𝑛𝑚 InGaAs cap and no chemical removal of residual oxides. 5_{Sample 𝐵 to 𝐷 (wafer C160420B): Hall bar samples of a deeply buried and undoped}

In0.75Ga0.25As/In0.75Al0.25As QW with 2.5𝑛𝑚 InGaAs cap and no chemical removal of residual

8 Ballistic conductance in InGaAs/InAlAs-based systems

hysteresis develops between up- and down-sweeps due to an increase in charge migration between QW and interface.

8.4 Conclusion

In this chapter, we demonstrated robust ballistic transport through our triple-gated QPC devices, defined in (InAs/)In0.75Ga0.25As/In0.75Al0.25As deeply buried 2DEGs. In these

samples, conductance characteristics of depletion and opening curves coincide and are highly reproducible. Furthermore, we are able to adjust electrically stable working points on the conductance curves even near channel depletion which is a clear proof of the efficient reduction of interface states in the heterostructures. In addition, the ballistic conductance can be essentially improved with the application of a positive CG-voltage, whereby the lateral confining potential is narrowed and deepend. This leads to a perceptible increase of the 1D subband spacing, which suppresses disorder-induced intersubband scattering and inhibits the creation of quasi-bound states. By shifting the QPC laterally in space via asymmetrically biasing the SG-electrodes, we are able to circumvent single scattering centers. Consequently, ballistic transport in the 1D channel can be further facilitated. For heterostructures, being equipped with an InAs inset inside the InGaAs QW and an InAlAs-terminated semiconductor surface, we determined the conductance steps to be less uniform than for InGaAs-terminated samples with a 20𝑛𝑚 InGaAs QW. Increased interface roughness due to the etching process and the reduced InAlAs spacer thickness are likely to generate an enhanced disorder potential, which adversely affects the 1D sublevel spectrum.

Although, we could eliminate the hysteretic behavior for deeply buried QW samples for both surface terminations, InGaAs and InAlAs, we find a pronounced shift of the pinch-off point between the depletion and the opening curve of the 1D channel for near surface QW samples. The charge redistribution during the pinch-off of the QPC confirms our model in which charge transfer from the 2DEG towards the interface is mediated by the InAlAs defect states. In addition, for highly conducting channels near the surface the conductance steps are obscured in comparison to samples with a deeper buried 2DEG. We attribute this observation to a more strongly disordered potential inside the QPC channel, owing to increased interface roughness. However, we want to point out that our experimental findings for samples C and D, studied in section 8.3, need yet to be substantiated by a relevant number of devices to gain statistical significance.

In conclusion, for the realization of robust 1D transport, we recommend to further optimize the MBE growth process in order to reduce the amount of deep level donor states inside the InAlAs spacer layers. This would be beneficial in two different ways: First of all, the potential fluctuations, introduced by the InAlAs defect states, would be minimized, whereby quasi-bound states inside the 1D channel could be reduced. This would lead to a general improvement of ballistic conductance. Secondly, band bending-induced charge transfer should be diminished, which would yield a more robust 1D transport in QPC devices.

Signatures of Rashba-type

spin-orbit interaction

9

In this chapter, the peculiar gating response of the heterostructure in gating areas II, III and IV, as introduced in chapter 7, is discussed. These gating regimes are characterised by a decrease of the measured 2D charge carrier density when the TG-voltage is increased. The physical origin of this behavior is well described by the charge transfer model, which we developed in the course of our 2D gating study in chapter 7. What we have left unaddressed so far are the observed undulations in the magnetooscillations in these particular gating areas, giving rise to a second frequency in the corresponding FFT spectra. This chapter serves to give a comprehensive discussion of this experimental finding. Furthermore, we give an estimation of the strength of Rashba-type SOI in the heterostructure via a self-consistent calculation of the band structure with a Schrödinger-Poisson solver in conjunction with calculations employing the envelope function approximation within the

k · p-method.

9.1 Gating response of undoped InGaAs/InAlAs