Planteamiento de Alternativas de Solución a Problemas

In this subsection, we will compare varactor-based approaches to active approaches, as well as different strategies using active approaches.

0 5 10 15 20 25 0.2 0.4 0.6 0.8 Ef fi ci e n cy [ % ]

"a" : (1-duty cycle)

1st-to-2nd harmonic conversion efficiency versus "a"

simulated 180GHz calculated (180GHz) simulated (220GHz) calculated (220GHz) -5 -4 -3 -2 -1 0 1 2 3 4 5 0.2 0.4 0.6 0.8 P o w e r G ai n [ d B ]

"a" : (1-duty cycle)

Fundamental Gain versus "a" simulated 180GHz calculated (180GHz) simulated (220GHz) calculated (220GHz)

To first compare varactor-based approaches with active approaches, we investigate the scaling of the various figures of merit with device size. In a short-channel approximation, will scale with the inverse of the gate length, as [17]

(3-19)

The product of the gate resistance and the gate-drain capacitance will similarly scale proportionally to the gate length. While we expect, the gate resistance for a given device width to scale inversely to gate length, shorter minimum device widths are typically available in more advanced technology nodes, leaving the overall gate resistance constant. Similarly, the gate-drain overlap capacitance should scale inversely to the gate length, offset by thinner gate oxides. However, oxide thicknesses are no longer decreasing linearly with the technology node. These assumptions, while somewhat oversimplifying the picture, still predict a scaling of inversely proportional to gate length, in accordance with observed data [44] as well as the ITRS technology roadmap [51].

For the MOS varactor capacitances, and , we can reasonably assume that they scale the same with the gate length. Hence, the varactor cutoff frequency will scale inversely to the product of device capacitance and gate/channel resistance. This product, for the same reasons as above, will scale approximately linearly with the device length; hence we deduce that the cutoff frequency of MOS varactors will be inversely proportional to the minimum available gate length in the technology. Thus, as CMOS processing technology advances to smaller minimum gate lengths, we expect no relative advantage of one approach over the other.

We can also gain insight into absolute differences between MOS varactor and active approaches by comparing cutoff frequencies achievable for MOS varactors versus

at a particular technology node.

We can bound the cutoff frequency by writing

( )

(3-20)

where ⁄ and . We express the product of as a ratio of to to obtain

( ) (3-21)

From this, we expect to be somewhat greater than . Typically, the ratio of on-to- off capacitance is close to or less than 2 (three-half typically), hence we expect the ratio of to to be comparable to the ratio of to . Thus, for any given technology

node, the core conversion efficiency of MOS varactors is expected to be higher than of any active circuit. This advantage, however, is typically more than offset by the higher required quality factor in the matching circuits. To illustrate this point, we note that – assuming that is constant but small – that efficiency is increased by increasing beyond all bounds. In this limit, the quality factor has a lower bound set by the product of

and , to wit

(3-22)

( ) (3-23)

Hence, the efficiency can only be increased by increasing the inherent quality factor of the varactor. Since the varactor needs to be matched at input and output, often several dB of additional losses are incurred compared to using an active circuit in the matching passives.

Using an active circuit, two different strategies can be pursued. The first strategy employs an oscillator. In order to derive the obtainable efficiency, we employ the same compression model as previously. We note that below , we feed back the

fundamental output power to the input. Thus, the oscillator duty cycle – and hence the generated second harmonic power – is determined by the duty cycle at which the fundamental power gain is reduced to one. Since the variables are related in a non- algebraic way, the solution cannot be expressed in closed form, but can be easily determined numerically. Namely, we set the fundamental power gain to 1 to obtain

(

)

(3-24)

from which we calculate (the numerical step), and from we obtain the drain efficiency, and, hence, the overall DC-to-second harmonic efficiency. This efficiency is only a function of the fundamental frequency, and is plotted in (on a logarithmic scale). We note that the theoretical efficiency increases as the oscillation frequency is decreased, as the DC-to-fundamental and fundamental-to-second harmonic conversion efficiencies both increase at reduced duty cycles.

We compare the simple oscillator topology with a topology of a driven oscillator: an oscillator driven with additional power of a second, fundamental oscillator. In this second scenario, it may become possible to drive to second oscillator deeper into compression using the power of the fundamental oscillator; hence additional degrees of freedom are obtained to maximize the DC-to-second harmonic conversion efficiency. With two oscillators (one driving and one generating), two variables exist: (1) the chosen duty cycle of the second oscillator (chosen such that the gain is less than one), and (2) the chosen duty cycle of the fundamental oscillator (gain greater than 1). The size ratio of the two oscillators can then be determined to be able to use any surplus power of the first oscillator to drive the second oscillator. For each operating frequency, we can find the optimum choice of the above two parameters, and compare the overall conversion efficiency to the conversion efficiency obtained from a single oscillator. The results are also plotted in Figure 3-17. For the second possibility (fundamental oscillator followed by a doubler), we again plot the conversion efficiencies, this time versus the duty cycle of the second oscillator (doubler). We only allow duty cycles that produce a gain of less than one, hence requiring the fundamental oscillator to provide additional conversion power. The results are shown in Figure 3-18. The horizontal lines mark the values obtained for a single oscillator (compare Figure 3-17).

Figure 3-17: Conversion loss (DC-to- second harmonic) for single oscillator (red) and optimized oscillator-doubler combination (black), assuming no DC conduction in doubler

Figure 3-18: Conversion loss (DC-to- second harmonic) for oscillator-doubler combination at =0.6max (black) and

=0.8max (red) versus doubler duty cycle. Lines are values for simple oscillator.

As is evident, a single oscillator always has greater conversion efficiency from DC to second harmonic power than any simple combination. This is intuitively clear, since the single oscillator subsumes the doubler, but may be run at higher drain efficiencies.

However, by observing the waveforms produced by the doubler carefully, we note that the doubler itself does not require DC power for high compression operation since the device provides very little gain, and no current flows for most of the period, thus negative voltages can be sustained while the device is off. We can recalculate the conversion efficiency, this time only accounting for the efficiency of the fundamental oscillator (without utilizing its harmonic output). Redoing the calculation, choosing values that maximize the conversion efficiency for both oscillator duty cycles, we obtain

-25 -20 -15 -10 -5 0.5 0.6 0.7 0.8 0.9 C o n ve rs io n L o ss [ d B ] Frequency/fmax

DC-to-Second Harmonic Calculated Conversion Efficiency Simple Oscillator Optimized, no DC -25 -20 -15 -10 -5 0.5 0.6 0.7 0.8 0.9 C o n ve rs io n L o ss [ d B ]

Duty Cycle of Doubler

DC-to-Second Harmonic Calculated Conversion Efficiency

w/wmax=0.6 w/wmax=0.8

the curve in Figure 3-17 (red curve). By comparison, for high operating frequencies, the conversion efficiency compared to the a simple oscillator is increased because the doubler can be driven deeper into compression without requiring unity power gain at the fundamental and using DC current. The optimal ratio as the frequency is increased is towards a larger fundamental oscillator and a successively smaller doubler.

Using this approach (not requiring the doubler to carry DC current) has another practical advantage: the maximum current densities for integrated devices are much larger for AC currents than for DC currents. Allowing only AC currents in the doubler allows the use of smaller metal lines in the layout, reducing parasitic device capacitances. Since at millimeter wave frequencies, capacitances as small as one femtofarad can significantly impact the overall conversion efficiency, such that reducing layout parasitics becomes important.

It must be mentioned, though, that separating the functions of providing fundamental power and performing the frequency conversion into separate devices inherently complicates the design, as additional matching passives are needed, introducing further losses and resulting in a less simple (and potentially less reliable) design. Having quantified and discussed these choices, however, gives us necessary insight for the designs to follow.