The major function of the clock d istribution chip (CDxx), shown in Figure 5, is to distribute master and reference clocks to each MCA on a multichip unit. There are eight pairs of differential master and
Di�ital Tecbuicaljournal 11Jl .! No. q Fa/1 1990
reference clocks. The chip also supplies clocks to all STRAMs on the unit. Each of t he STRA M 's four groups of SL'< clocks can be programmed to one of eight possible clock phases. This flexibility in pro gramming al lows the system designer to select the appropriate clocks for STRAMs in order to meet system timing requirements.
In addition to prov iding the functions above, the design goals for the CDxx project included the fol lowing:
• Minimize the space occupied by the chip on the mul tichip unit
• Provide scan control and scan distribution
• Include a wideb:md amplifier
• Ensure low clock skew
• Provide a temperature-detecting circuit
VBB1 VBB1
VBB3
vee
ONE LEVEL OF GATING
vee
THREE LEVELS OF GATING Figure 4 Two-leuel Functions uersus Three-leuel Functions
Semiconductor Technology in a High-pe�tormance VAX Syste�n
HOT CIRCUIT
Figure 5 Photomicrograph of CDx.-.: Chip Minimizing the real estate occupied by the chip
was comp licated by addi tional functions located on the CDxx, such as scan and the temperature detect ing circuits. The minimization was accomplished by employing a custom chip design approach in which each element (cell) is optimized and then manually placed and routed to achieve a compact design. As it turned out, the size of the chip was not determined by the amount of real estate needed to implement the circuits, but rather by the number of pins required to communicate to the rest of the multichip unit.
Since a CDxx is mounted on every multichip unit i n the CPU, the scan distribution and control logic are located on this chip. The CDxx chips i n the sys tem are chained together on the system scan bus.
Digital Tecbnicaljournal Vol. .! No. ·I Fall I'J'JO
Each coxx receives its scan control signals from the previous CDxx in the chain or from the service pro cessor. As shown in Figure 5, there are three scan rings located on the CDxx. Ring 1 2 is a 16-bit ring reserved for the CD)C'< STRAM clock generation con trol ring. This ring controls the STRAl'•l clock phase selection and enable for each of the four STRAM clock groups. Ring 1 3 is a 14-bit ring reserved for the CD)C'< scan control. Data is shifted into this ring and then loaded i nto CDxx control registers. Ring 14 is a 47-bit r ing reserved for the CDxx information scan ring. Data is loaded into this ring from CDxx data registers and shifted out ro the service processor.
The design of the w idebaml amplifier was prompted by the need for the clock distribution chip to receive two differential sinusoidal master
and rcfc.:n:nce c lock signJis as inpurs. These.: signals arc.: transformer coupled from the clock source. The master clock runs at one L"ighrh the systL"m cycle rimL". and the reference clock runs at the sys tem ncle rime. The wideband amplifier receives differential s inusoidal signalls of relatively small amplitude - less than 125 milli\·olts peak to peak and transforms them ro lOOK ECL levels on output . Th<.: design of the input circuits meets these crite ria and rypic::�lly functions with inputs less rhan 65 mi llivolts.
All rhe clocks are distributed by the COxx as pairs of diffcrc:ntial signals. The distribution of these clocks is, of course, ro be done with minimal clock s kew. Clock skew is the difference in del::�y time berw<.:c:n di fferent clock outputs measured from a com mon point. The common point in this case is the numbc:r of master dock inputs to the chip. To maintain low clock skew, technologists designed fast gates and minimized the number of cascaded gates in the clock path. A lso, all the metal that inter connects the cel ls in the clock path is controlled for equal delay. As a resu lt, the measured clock skew is less than 100 picoseconds on a chip for master, reference, and STRAM clocks. The delay of master clock input ro output is less than I nanosecond (ns).
The: temperature-detecting circuit on the CDxx warns rhe system when a device junction tempera ture approaches rhe maximum allowed tempera tun: on a m u ltichip unir. As i m p lemented, t he circuit is controlled from t he system console. The console loads rhe CDxx with a number that repre sents rhe temperature rhe circuit musr use as a point of comparison . If rhe junction temperature of rhe Cl)xx is higher than the programmed value, the cir cuit trips and notifies the console of a temperature problem. The console rhen rakes corrc.:crive acrion.
Self-timed Register File Chip - STGx
The self-rimed register file chip (sn; x ) is employed in the VAX 9000 to provide four register banks accessible through muhirle read and write pons. ·rhe four banks incluJe a microcode scratch-pad register hank, rhe VA X generJl-purpose register set, a memory Jara register storage bank , and an instruction data register ban k . The performance requirements for rhe STC x were quite rigid and guided several key design tkcisions, including den sity and layout. The read access time was ro be less than ':i ns. The write access time was to be less than 6 ns. Ln orher words. rhe chip must read or write any one of irs 6.:j locations in ':i or 6 ns. respectively. Borh goals ha\'e been met . In fact. rhe read access
time is typically less rhan 4 ns, and rhe write time is typically less rhan ':i ns. Figure () is a photomicro graph of the STG x chip.
The STGx is a 64 -word by 18-bit LCL register file containing three wrire ports and rwo read ports. The 64 words are separated into four 16-word by 18-bit storage array sections. Each of the four stor age banks has dual read capabi lity. Storage bank one has dual write capability; storage banks rwo and three have triple write capability; and storage bank four hJs single write capability. Simultaneous write access to the array is possible through a l l pons wirh correct results occurring; the only except ion is in the case of writes to the same location from multi ple pons, which is an undefined operation. A write followed by a read access to the array - even to rhe same address - is possible w irh correct results occurring. The chip has two clock inputs for con troll ing reads and writes.
One requirement for rhe design was to include a self-rimed write capabil ity so that the system need nor provide properly timed write pulses ro rhe chip. In rhe system, rhe chip is clocked with STRAM clocks for reading and writing. The design uses these clocks to latch read address information, to latch write add ress information, and to latch input data. In addition, the design rakes the leading edge of the write clock ro generate a delayed write pu lse. The delayed write pu lse is used to write the appro priate word in the 64-word by 18-bir array, raking into account rhe rime needed ro decode the wri re address.
The design sryle used to implement r he self-rimc.:d register file chip is s imiiJr ro a sil icon compiler tech nique. The chip's storage area is made up of four arrays. The input add ress register for borh read and wrire ports, the inpur dara larches. and rhe dat::l out pur drivers are arrangements of c<:l ls in strips. The placement and routing of these arrays and strips was procedurally performed using custom layom tools. Once rhe blocks were: assembled and p laced, inter connecrions among blocks, strips, and pins were then routed manually.
Multiplication Chip -MULx
The architecture of the scalar processor defined an integrated floating point p rocessor. U n l i ke most RISC processors, which off-load all floating poinr operations ro a separate tloating point processor, rhe VAX 9000 sysrem handles floating point opera tions within the E-box. 1 The multiplication unit therefore supports horh inr<:ger and tloaring point formats. To ach ieve this support, a custom chip was
Semiconductor Technology in a High-JH!r(ornwnce VAX -�),stem
Figure G Photom icrograph ofSTGx Chip required that provided superior performance. spe
cial logic gates. and improved density. Custom chip tech nology provided enough dcnsity to accommo date a .12-bit by :)2-bit. cight-logic-l<:vcl multiplica tion array in a singlc chip ( M l l l . x). To mini mize the cost and time of custom design . designers employed standard cell design techniques in which the cell height was fixcd anu thc width cou ld vary to take advan tage of packing dcnsit y. By constraining
the design i n this fashion. the H igh Performance Systems Group's < .AD suitc cou ld be employed to p l ace and rou te the c h i p . Special logic gates eliminated t hrcc logic lcvds. and h igh-powered fast gates provided t he pnfmmancc to perm i t a .12-bit by :)2-bit multiph· opcra t ion in less t han 9 ns. Fig un: I shows a photomicrograph of t ile \l l l. x chip.
Digital Tecbnicaljournal \i,f . .! .\iJ. 1 hiii i'J'Jii
Three �l l ' L x chips werc r<:quired in the scalar
processm to achieve doubk-prcc ision r<:rformancc in which every 64 ns a ')6-bit mul tipl ication could complete. Each M l ' l . x chip has two .12-bit i n put data
buses. The M l ! L x chip is also employed to perform
all i nteger multiply operations in a single 16-ns cycle.
The scal::ir processor, which has .12-bit-wide data paths, delivers double-precision input data in two cycles. In the first cycle, each M l lLx consumes the most sign ificant high bits of c:Kh operand . A II three
MULx chips latch this <.bta while also u n pack i ng it, multiply ing it, and then latching the product. One of the M l ' L x chips' results is then s:1ved . In the second cycle. the n.:maining dou hk:-prccision dat:I, t he least significant low bits. is consumed , and each
-- -.
M U LT I P L I E R ARRAY
Figure 7 Photomicrograph ofM UL:x Chip
MULx chip unpacks the data and performs a unique multiply: operand A high bits and operand B low bits; operand A low bits and operand B h igh bits; and operand A low bits and operand B low bits.
A n 1\KA I I I gate array accumul ates a l l these
results, and another rounds and packs the bits into a
VAX floating point product. Since each ivl ULx needs ro know which partial product it must compute in the second cycle, two personality bits are included that are loaded by means of the system scan chain .
M U Lx chips are also used in the vector processor. The vector processor (V-box ) has 64 -bit-wide data paths. Four MULx chips are emp loyed ro complete a double-precision multiply every 16 ns. Since the operand unpacking di ffers between the scalar and vector processors as a result of how fast operands
52
are delivered, each MLJ L x has an additional person ality bit for indicating whether the MULx is in the V-box or E-box.
The MULx chip, as used in both the scalar and vector processors, is a 32-bit by 32-bit ECL parallel multi plier which is fully pipelined for a 16-ns cycle time. It performs both two's complement and sign/ magnitude multiplication. In a single cycle, the chip unpacks VAX float ing point formats F, D, and G, or i nteger formats long, word, and byte; performs exponent calculations and sign handling; and com pletes up to a 32-bit by 32-bit multiplication.
I f the operation is double precision, the 64 -bit result is a partial result. It must be accumu lated with three other partial results to form t he double-preci sion, correctly rounded, and normalized product.
Semiconductor Technology in a High-performance VAX System
If the operation is an integer type, then the 64-bit two's complement result is the VAX integer product. A long with producing this integer product, MULx also produces the correct condition codes. Integer operations require one machine cycle to complete. Operands are not latched at input . Instead they are immediately unpacked and sent to the multiplica tion array. This multipurpose array then produces a set of sum and carry product vectors. These vectors are then added in a ful l carry lookahead adder (CLA). This adder comprises a 31 -bit adder and a 32-bit adder, cascaded . The produced sum is the 64 -bit product, which is then latched. The output of the latch is used to compute i nt eger-type con dition codes.
The integer instructions supported include VAX MULB , MULW , and MULL. EMUL is also directly sup ported, along with the Z and N bit condition codes. Finally, to assist in H format-type multiplications, a true 32-bit by 32-bit magnitude mu ltiplication is also supported, called EXTMU L (extended multiply). There is a 64 -bit data path back into the E-box for EMUL- and EXTMUL-type operations.
Six features of the M U Lx design that improve per formance and minimize logic should be noted . First, unlike traditional designs, the MULx design does not include Booth recoding of the multiplier operand . Booth recoding offers no logic savings either in timing or real estate when the multiplica tion array reduction scheme is optimal. Second, a Baugh-Wooley two's complement algorithm was used to implement integer multiplication .' Third, engineers designed special full adder logic gates to integrate multiplication summand generation into the full adder cel l and to eliminate the need for an additional logic level. Fourth, a unique multipli cation reduction algorithm was developed which provides the initial routing advantages of a Wallace tree, with the minimal logic of a Dadda tree."·6 Fifth, a ripple is formed in the reduction array. The ripple facilitates the start of the least significant 31 -bit CLA addition at least one logic level sooner than the most significant 32 bits and does not require a carry-in input to the upper 32-bit adder. Finally, by developing a very fast 4 -3-2 - 1 A N D/OR gate, engi neers were able to remove two additional logic levels in both CLA adder networks.
To avoid bugs in the array design, since bugs in an array consisting of 1000 full adders could have sig nificantly affected the product shipment schedule, engineers developed a FORTRAN program to logi cally interconnect and physically place the array.
Any bugs would be algorithmic and not random, and algorithmic bugs should be obvious. In addi-
Digital Tecbnicafjournuf Vol. 2 No. 4 Fall 19')1!
tion, by algorithmically placing the array, signi ficant density improvements were realized . This program provides a Wal lace-Dadda implementa tion that logically reduces 32 rows in 8 logic levels, and consumes as many initial summand bits. It also uses the least number of full adders as theoreti cal ly possible, while delivering the least significant 32 bits of sum and carries at least one full logic level sooner than the most significant bits.