The iterative divide function performed by the divi sion chip , DIVx, requ i res a signi ficant amount of hardware, the density of which a standard cell chip affords. Two gate arrays would be required to per form the same function, in which case a timing critical path crossing would occur between the two chips. Therefore, the IC designers implemented the DIVx chip as a standard cell design by building on the techniques developed for the MULx chip described above. Also, like the MULx design, the goals for the D!Vx design project were to optimize performance and minimize real estate use by fitting t he iterative divide function in a single chip.
The IC designers employed a standard cell tech nique in which four horizontal sections are defined , each section having a different number of columns. Reference cells are located in the center row of each section and provide ECL reference voltages to the cells above and below i n that section 's columns. Placement was driven for performance, with quo tient selection logic being distributed to where i t was required. This method made for a n irregular structure, as can been seen in Figure 8.
The VAX 9000 system optimizes both mu ltiplica tion and division by providing separate functional units. Each functional unit performs both integer and floating point operations. This approach differs from the one taken by most processor architects, who conceptually link multiplication and division . Usually, algorithms are chosen that can share hard ware at the expense of the performance of either operation. The separate division unit in the 9000 provides superior performance for both i nteger and floating point operations. The DIVx chip is also used by the V-box to perform very fast vector divi sion operations, as shown in Table 4 .
Division is an iterative process. Unlike the case of multiplication, one cannot predict the summands and then reduce the summand matrix. The two approaches to division most commonly used are the Taylor Series convergence algorithm and a sub tract and shift algorithm.� The algorithm employed in the 9000 is a variation on the subtract and shift
Table 4 Division Performance Time
Data Type Cycles (Nanoseconds)
Integer: byte 3-4 48-64 word 3-5 48-80 long 3-8 48- 1 28 Floating point: F-format 7 1 1 2 D-format 1 3 208 G-format 1 2 1 92
method, which allows for savings in hardware as well as increased performance.
Jn this method, an imprecise quotient is selected based on a truncated estimated partial remainder
and a truncated version of the exact divisor. This imprecise quotient digit is corrected when the next guess quoticnt digit is selected . The selected digits may be positive or ncgative. The positive digits are accumulated in a positive-value shift register. The negative digits are accumulated in a negative-value shift rcgistcr. The final corrected binary quotient is then formed by subtracting the negat ive register from the positive register.
The algorithm is based on a signed d igit notat ion scheme. To determine two quotient bits, the bits may be chosen from a d igit set that i nc ludes
{ -2, - I , -0, + 0, + 1, + 2 }. The digit set is simply an expanded form of the common nonrestoring digit set that typically uses { - 1 , 0, + 1 } . In nonrestoring algorithms, the quorient is normally corrected as
Figure 8 Photom icrograph of D!Vx Chip
Semiconductor Technology in a High-performance VAX System
needed; whereas here, it is not corrected u ntil the entire iterative process is completed . The next sig nificant difference between this division technique and the nonrestoring method is that the quotient bits selected are based on an estimate of the partial remainder and divisor rather than the exact values. The first advantage of this method is that an esti mate can be obtained faster than the exact value. Second, a truncated estimate is acceptable, rather than a fu ll-width estimate. Consequently, this method saves a significant amount of hardware and increases the speed of the operation . If one were to complete each partial remainder, up to three addi tional chips would be required and the delay would more than double.
The trick to the method lies in the quotient selec tion . The selection is based on partial remainder range transformations which guarantee that a quotient digit selected in one iteration may be cor rected to the exact quotient digit on the next iteration. Therefore, although six quotient digits are determined per major iteration, an additional minor iteration is required to guarantee the least significant digit of the major iteration. The major and minor iteration terms refer to the architecture of the divide iterative hardware. The OIVx produces six quotient bits per machine cycle. This is a radix 64 division technique. However, the high radix division is accomplished by overlapping lesser radLx divisions. In particular, there are three sets of radix 4 division groups. The first two sets are over lapped, so that the critical path t hrough the radix 64 division is actually the critical path through two radix 4 divisions. A m inor iteration is the path through one radix 4 division group. A major itera tion is the path through the overlapped set of two radix 4 division groups, followed by the final radix 4 group. It is important to note that extra iterations do not adversely affect the corrected quotient. Final ly, to produce the corrected quotient, the set of negative quotient digits is subtracted from the set of positive quotient d igits, where each digit is properly radix 2 weighted, based on the order of selection. (That is, the first quotient digit selected is the most significant bit of the correct quotient.)