in a High-performance
VAX System
The VAX 9000 system is the newest member of Digital's VAX family of computer systems. The 9000 is a high-performance ECL processor, with a very fast, 16-nano second cycle time. To achieve this high level of performance, a new generation of semicustom and custom integrated circuits was required for the scalar CPU and the vector processing option. Goals for circuit density, performance, and skew mainte nance were fulfilled with the development of a high-speed gate array, special custom chips used in key applications, and a high-speed RAM employing a new architecture.
The semiconductor requirements for the VAX 9000 system posed a number of challenges for Digital's Integrated Circuits Development Group. Those requirements included a tremendous number of equivalent logic gates ( 1 ,037,4 00 gates) and a large amount of RAM in the processor (3,280,000 bits). Moreover, the project 's performance goal of over 30 VAX- 1 1 /780 units of performance (VUPs) required the development of state-of-the-art semi conductors and the use of innovative techniques to design them .
G iven the project's goals, the IC technologists evaluated several competing semiconductor tech nologies and decided to i mp lement most of the logic within the 9000 system in a h igh-speed, high density, 10,000-gate array. The gate array provides a broad range of speed and power-dissipation options. Working with Motorola, the IC Group first engineered the base 10,000-gate macrocell array (MCA), which is implemented in Motorola's MOSA IC III process. Logic engineers then designed the 77 d i fferen t gate array chips (options) on the base array, using a rich library of logic functions and a set of automated place and route tools. Additiona lly, they designed five custom chips, invented a fast cycle time, self-timed random access memory (STRAM) architecture, and designed a multichip unit to imerconnect all these high-performance !Cs. '
Four different design methods were used to
implement the chips. The MCA x chips employ a gate
array design technique. The cnxx, the V RGx, and the Sl"RAM chips required a full custom approach .
Digital Technicaljournal Vol. .! No . .:j Fall /')90
The STGx chip was implemented using a silicon compiler technique. T he M ULx and DJVx chips mwere implemented using a standard cell design approach. Statistics on 9000 system chip design are given in Table 1 .
This paper describes the VAX 9000 MCA Ill gate array, the development of each of the five custom chips, and the STRAM architecture. Before our dis cussion of the gate array, we present a brief overview of the semiconductor technology used to fabricate the array and the custom chips.
Semiconductor Technology
In 1985, the VAX 8800 series was D igital's largest and most powerful system, offering single-CPU per formance of eight VU Ps. The 8800 CPU logic was Motorola's Macrocell A rray I (MCA I ) gate array, which was fabricated in MOSAIC I bipolar technol ogy. In comparison, the VAX 9000 goal of 30 VlJPs was aggressive, and the IC Group realized a new semiconductor technology was required .
At the start of the project, the technologists evalu ated semiconductor vendors to determine what was the "best" technology available to implement the new system. CMOS , BiCMOS, bipolar, and GaAs IC technologies were evaluated. Among the factors considered were logic density, gate delays, on- and off-chip interconnect delays. mam.1facturing risks, and prod uct delivery.
Although very high gate densities were available with CMOS technology, the logic gate delays proved
Table 1 VAX 9000 Chip Statistics
Die Size
Chip Description (Milli meters)
MCAx MCA I l l gate array chip 9.8 X 9 . 8 CDxx Clock distribution chip 6.2 X 6.2 STGx Self-tim ed reg ister file chip 9.8 X 9.8
M U Lx M u ltiplication chip 9.8 X 9.8
D IVx Division chip 9 . 8 X 9.8
VRGx Vector register file chip 9.8 X 9 . 8
1 KSR 1 K x 4 self-ti med RAM 4.9 X 3.6
4KSR 4K x 4 self-ti med RAM 6.4 X 4.2
to be too slow ro meet the cycle time requirement. Also, the CMOS output circuits could not drive sig nals off-chip i nto a 50-oh m transmission l i ne as quickl y as a bipolar transistor, which l imited the speed of signal between IC:s.
B iCi\·JOS offers the advantage of h ighly dense
CMOS coupled with bipolar drive capability. How
ever, the technologies available at the time were optimized for the best CMOS transistors with a com promised bipolar device. This approach l imited the overall performance of the circuit to a level roughly equiva lent to that of previous generation bipolar devices, which would not be aggressive enough ro meet the CPU performance needs.
Gallium arsenide (GaAs) ICs offer a theoretical performance advantage of between two and three to one over s)licon implementations. The group found IC densities were lower than those of bipolar devices, however; and the on-chip speed advantage was countered by the need for more off-chip sig nals in the critical paths of the C P U . A lso, because the manufacturing technology of GaAs ICs was immature, very few companies had attempted to sell GaAs into the commercial marketplace. So while this technology was considered for a rime in some applications where alternatives also existed, GaAs were eventually dropped from consideration because of the uncenainty of availability.
The IC Group also studied Motorola's third generation of their oxide-isolated self-aligned implanted circuits (MOSAIC I l l) bipolar technology.2 Ir offered a factor of six in speed advantage over the prev iously used MOSA IC I technology and had the potential of prov iding eight to ten times the logic density. Although not as dense as CMOS or BiCMOS, MOSAIC I ll was much faster than either of those technologies and much denser than any avail able GaAs technology I n addition, although many
44
Signal Transistor RAM Power
Pins Count Bits (Watts)
256 40. 1 K 30 1 70 7.2K 1 3.9 1 52 29.3K 1 7 . 8 1 82 48.4K 30.9 1 1 2 29 .2K 23.9 1 98 76.0K 92 1 6 24.9 33 28.0K 4096 2.4 35 1 03 .0K 1 6384 2.4
of the manufacturing steps were new, most of them were based on previously proven techniques. The group therefore concluded that MOSA IC 1 1 1 was best suited tO meet the challenges of the VAX 9000 system.
The MOSAI C Ill process is an advanced silicon
bipolar process which yields a transistor structure with a polysilicon base. emitter and collector elec t�·odes, pol ysi licon resistors, and three layers of metalization. Compared to the MOSAIC l device used in the 8800, the critical col lector-base junction of this transistor structure takes up approximately 50 percent less area, as shown in Figure I. Com bined with shallower junctions and reduced base resistance, the intrinsic device performance was improved by a factor of three. Further, the poly silicon resistor produced with this process has far lower parasitic capacitance than the MOSA IC l
monosilicon resistor. Some key performance mod eling parameters and density metrics are provided with the figure.
The VAX 9000 packaging imposed other require ments on the semiconductor technology. Power dissipation increased from 5 watts for the MCA I to �0 watts for the MCA I ll because of the increase in gate density from 1 , 200 to 10,000 gates. Therefore it was determined that all chips should be mounted directly to the multichip unit cold plate for opti mum cooling. For manu facturing economy, it was desirable to bond the multiple leads of the chip directly to the pads on the h igh-density signal car rier (HDSC). Consequently, all CPU chips must be provided to the mul tichip unit assembly site in a tape automated bond (TA B) package. As shown in Figure 2, chips are mounted in a plastic carrier suit able for automated handling, and the surface of the die is protected from mechanical damage with an epoxy encapsu lent.
Semiconductor Technology in a High-performance VAX System