I N S T I T U T O TECNOLÓGICO Y D E ESTUDIOS SUPERIORES D E M O N T E R R E Y
C A M P U S M O N T E R R E Y
P R O G R A M A D E G R A D U A D O S E N TECNOLOGÍAS D E I N F O R M A C I Ó N Y E L E C T R Ó N I C A
Programmable Multichannel Sine Wave Generator for a C - M E M S Based Dielectrophoretic Filter
TESIS
P r e s e n t a d a c o m o requisito parcial para o b t e n e r el grado de
Maestro en Ciencias en Ingeniería Electrónica con Especialidad en Sistemas Electrónicos
Por
Jorge Andrade R o m á n
M o n t e r r e y , N . L . D i c i e m b r e , 2 0 0 8
Instituto Tecnológico y de Estudios Superiores de Monterrey
Campus Monterrey
División de Tecnologías de Información y Electrónica
P r o g r a m a de G r a d u a d o s
Los miembros del Comité de Tesis recomendamos que la presente tesis de Jorge Andrade Román sea aceptada como requisito parcial para obtener el
grado académico de M a e s t r o en Ciencias e n Ingeniería E l e c t r ó n i c a c o n e s p e c i a l i d a d e n S i s t e m a s E l e c t r ó n i c o s
Sergio O. Martínez Chapa, P h . D . Cuauhtémoc S. Carbajal Fernández, P h . D .
Comité de Tesis
Asesor principal Co-asesor
Alfonso Ávila Ortega, P h . D . Sinodal
Graciano Dieck Assad, P h . D . Sinodal
J o a q u í n A c e v e d o M a s c a r ú a , P h . D . Director del P r o g r a m a de Graduados en Tecnologías
de Información y Electrónica
M o n t e r r e y N . L . , D i c i e m b r e de 2 0 0 8
Programmable Multichannel Sine Wave Generator for a C - M E M S Based Dielectrophoretic Filter
Por
Jorge Andrade Román
TESIS
P r e s e n t a d a al P r o g r a m a de G r a d u a d o s de la D i v i s i ó n de T e c n o l o g í a s de Información y E l e c t r ó n i c a c o m o requisito parcial para o b t e n e r el grado de
Maestro en Ciencias en Ingeniería Electrónica con Especialidad en Sistemas Electrónicos
Instituto Tecnológico y de Estudios Superiores de Monterrey
Campus Monterrey
M o n t e r r e y , N . L . D i c i e m b r e , 2 0 0 8
Dedicatoria
A mi hermana Tere, por ser mi mas grande motivación y mi fuente de inspiración para realizar este trabajo, por toda tu fuerza y valor ...
A mi mama Tere, porque soy quien soy y hago lo que hago gracias a ti, por ensenarme a ser un hombre de bien, por tu apoyo incondicional, por tu amor y comprensión hacia Tere y a mí...
A mi querida Paloma, por tantos años de amistad desde la Univer¬
sidad, por toda tu atención, cariño, comprensión, y por el amor que me has brindado ...
sin ustedes no habría sido posible.
Jorge
Agradecimientos
Al Dr. Sergio O. Martínez, por confiar en mí para el desarrollo de este trabajo, y por su apoyo durante mi estancia,
Al Dr. Alfonso Ávila O., por creer en mi capacidad desde que ingrese al programa de maestría, y por todo su apoyo,
Al Dr. Graciano Dieck A., por sus acertadas observaciones y sus sugerencias en la redacción de este documento,
Al Dr. Cuauhtémoc Carbajal F., por sus consejos al inicio de este trabajo y por sus observaciones en la redacción,
Al Dr. Mark Madou, por encabezar esta importante línea de inves- tigación,
A Rodrigo Martínez D., por su apoyo con información sobre la apli¬
cación, y por sus atenciones en California, U.S.A.,
A Ever Eli, por su apoyo en la fabricación de los módulos analógicos del prototipo,
Al Dr. Mariano Aguirre H., por su orientación en la elección de mis estudios de maestría, por sus consejos, confianza y amistad de tantos años,
A mis compañeros y amigos que siempre me apoyaron durante mi estancia en el Tec,
A mis profesores, porque aprendí de ellos, A mis alumnos, porque aprendí con ellos,
... y a todos aquellos que siempre han estado conmigo, Muchas Gracias
Jorge Andrade Román (ARJ)
Programmable Multichannel Sine Wave Generator for a C - M E M S Dielectrophoretic Filter
Abstract
Jorge Andrade Román
Instituto Tecnológico y de Estudios Superiores de Monterrey, 2008
Thesis advisor: Sergio Omar Martínez Chapa, Ph.D.
Co-advisor: Cuauhtémoc S. Carbajal Fernandez, Ph.D.
This thesis develops a programmable multichannel sine wave generator for a C - MEMS dielectrophoretic filter in order to separate bio-particles.
Independent frequency generation is obtained using the direct digital frequency synthesis technique, implemented in a F P G A chip. To synthesize sine waves, sym¬
metry has been exploited. And memory requirements were reduced. Sine wave pa¬
rameters are programmed through a RS-232 to SPI interface of a personal computer and F P G A . A prototype consisting of two channels is implemented developing two external modules from F P G A . A frequency resolution of 2.980232Hz is obtained, and a maximum of 12.5MHz may be generated per channel. Digital amplitude control is implemented either with a 0.087Vpp step resolution, capable to create sine waves up to 22.4Vpp on each channel.
Contents
List of Tables vi
List of Figures viii
1 Introduction 1
1.1 Dielectrophoresis . . . 1
1.2 Problem Definition . . . 1
1.3 Objectives . . . 3
1.3.1 General Objective . . . 3
1.3.2 Particular Objectives . . . 3
1.4 Hypothesis . . . 4
1.5 Justification . . . 4
1.6 Contribution . . . 4
1.7 Document Organization . . . 4
2 Direct Digital Frequency Synthesis 5 2.1 Introduction . . . 5
2.2 Basic DDFS Form . . . 6
2.3 Complete DDFS Form . . . 7
2.4 Sine Wave Generation . . . 9
2.5 Phase Quantization . . . 13
2.6 Amplitude Quantization . . . 16
2.7 Data Compression . . . 18
2.7.1 One Half Sine Symmetry . . . 19
2.7.2 One Quarter Sine Symmetry . . . 21
3 Digital Stage Implementation 23 3.1 Introduction . . . 23
3.2 Data Transfer (RS232–SPI) . . . 26
3.2.1 Programming Word Format . . . 27
3.2.2 Data Protocol Adjustment . . . 28
3.2.3 Microcontroller to FPGA Interface . . . 31
3.2.4 FPGA to Microcontroller Interface . . . 34
3.3 SPI Load Module . . . 36
3.3.1 Channel Selector Decoder . . . 38
3.3.2 Frequency Tuning Parameter . . . 39
3.3.3 Voltage–Amplitude Section . . . 40
3.4 DDFS Engine . . . 41
3.4.1 Phase Accumulator . . . 41
3.4.2 One Quarter Sine Wave Data Block . . . 43
3.5 FPGA Data Input/Output . . . 48
4 Analog Stage Implementation 49 4.1 Introduction . . . 49
4.2 Amplitude Controller . . . 50
4.2.1 Single–Ended Current to Voltage Conversion . . . 52
4.3 Sine Wave Reconstruction . . . 53
4.3.1 Differential Current to Voltage Conversion . . . 55
4.4 Filtering . . . 58
4.4.1 High Pass Filter . . . 59
4.4.2 Low Pass Filter . . . 59
4.4.2.1 Inductors Implementation . . . 63
4.5 Output Stage . . . 65
4.5.1 High Speed Power Amplifier . . . 65
4.6 Final Modules Implementation . . . 66
5 Tests & Results 69 5.1 Introduction . . . 69
5.2 FPGA Statistics . . . 70
5.3 Simulation & Programming Software . . . 72
5.3.1 Simulation Results . . . 73
5.4 Variable Reference Voltage . . . 75
5.5 Sine Wave Generation . . . 76
5.6 System Frequency Response . . . 77
5.7 Independent Channels Operation . . . 81
6 Conclusions & Recommendations 83 Bibliography 87 Appendix 91 A Codes & Circuits 91 A.1 Microcontroller Data Conversion . . . 91
A.2 DDFS Matlab Simulation & Programming . . . 98
A.3 ROM Data Generation . . . 101
A.4 FPGA Implementation Schematics . . . 103
A.5 FPGA UCF File for I/O Location . . . 112
A.6 External Modules Schematics . . . 113
A.7 External Modules Layouts . . . 116
List of Tables
2.1 Number of points for N –bits (2N) . . . 11
2.2 Truncated 6–bit to 4–bit wheel output with M = 3 . . . 15
2.3 Computed sine wave for n = 8 & Q = 4 . . . 17
2.4 Half sinusoidal wave for n = 8 & Q = 4 . . . 20
3.1 Equivalent ASCII characters hexadecimal values . . . 28
3.2 Functions of each pin in the µC . . . 32
3.3 Assigned pin functions in µC board . . . 35
3.4 Truth tables for controlled serial loading . . . 37
3.5 Truth table for decoder implementation . . . 38
3.6 Controlled inverter truth table . . . 44
3.7 Data stored in memory blocks . . . 47
4.1 FPGA pin–out location for channel–0 amplitude controller . . . 51
4.2 FPGA pin–out location for channel–1 amplitude controller . . . 51
4.3 FPGA pin–out location for channel–0 sine wave reconstruction . . . . 54
4.4 FPGA pin–out location for channel–1 sine wave reconstruction . . . . 54
4.5 Determined elements for the low–pass filter . . . 62
5.1 Frequency vs maximum amplitude measurements . . . 78
Ω
List of Figures
1.1 Particle in a non–uniform electric field . . . 2
1.2 Schematic drawing of multistage CarbonDEP system . . . 2
1.3 Multistage dielectrophoresis filter device . . . 3
2.1 Simple form of a direct digital synthesizer . . . 6
2.2 Complete form of a direct digital synthesizer . . . 7
2.3 Phase accumulator behavior with 4 bit resolution for M = 1 and M = 3 8 2.4 A digital phase wheel with 4 bit resolution . . . 9
2.5 Transfer from a digital phase with 4 bit resolution to a sine wave with M=1 . . . 10
2.6 Transfer from a digital phase with 4 bit resolution to a sine wave with M=3 . . . 10
2.7 Proposed filter response for a DDFS output . . . 12
2.8 Sine wave generated by a non truncated & truncated phase wheel . . 13
2.9 DDFS System with phase truncation from N to N − P bits . . . 14
2.10 Phase wheel (with 6 bit resolution) truncated to 4 bit with M=3 . . . 14
2.11 Simulated outputs for non-truncated & truncated phase wheel with M=3 15 2.12 Relation from a phase angle φT to an amplitude value A[φT] . . . 16
2.13 MATLAB simulation for a quantized sine wave with n = 8 & Q = 4 . 17 2.14 Rotation over the phase wheel to explode symmetry . . . 18
2.15 MATLAB simulation for a rotated sine wave with n = 8 & Q = 4 . . 18
2.16 Sine wave generation using half symmetry . . . 19
2.17 Sinusoidal wave with n = 8 & Q = 4 using half symmetry . . . 20
2.18 Block diagram of the one quarter symmetry method . . . 21
3.1 Methodology for the DEP research . . . 23
3.2 Block diagram of the complete prototype . . . 24
3.3 Complete multichannel sine wave generator . . . 25
3.4 Digital boards corresponding to the working prototype . . . 25
3.5 Proposed programming word format . . . 27
3.6 Flow chart for the RS232–SPI conversion . . . 29
3.7 Flow charts for a) ASCII to Hex Conversion b) Nibbles swapping & mixing . . . 30
3.8 Microcontroller interface schematic . . . 31
3.9 RS–232 to SPI data connector location . . . 32
3.10 PC layout of transceiver with multiple voltages power supply . . . 33
3.11 Transceiver & power supply board . . . 33
3.12 Spartan–3E development board used for the generator . . . 34
3.13 RS–232 FPGA board connector configuration . . . 35
3.14 Cable connection between µC & FPGA board . . . 35
3.15 SPI mode waveform from µC to FPGA board . . . 36
3.16 Serial to parallel conversion . . . 36
3.17 Controlled serial to parallel conversion . . . 37
3.18 Block diagram for the shift register division . . . 37
3.19 Decoder for channel selection from Ch0 to Ch3 . . . 38
3.20 Data registers for independent M parameters . . . 39
3.21 Data registers for independent amplitude setting . . . 40
3.22 Implemented design for the DDFS phase accumulator . . . 41
3.23 Basic representation of ROM stage . . . 43
3.24 Internal blocks of ROM stage . . . 43
3.25 Implemented topology for the controlled inverters . . . 44
3.26 Implementation of the 29× 10 bit–size look–up table . . . 45
3.27 One quarter sine wave data stored in memory . . . 46
3.28 Synthesized (digital) sine wave . . . 46
3.29 Spartan–3E XC3S500E–PQ208 chip . . . 48
4.1 Prototype boards corresponding to the analog implementation . . . . 49
4.2 Variable reference voltage generator for channel–0 . . . 50
4.3 DDFS sine wave DAC converter for channel–0 . . . 53
4.4 Differential amplifier configuration . . . 56
4.5 Sine wave output for VXREG =“11111111” (255) . . . 57
4.6 Sine wave output for VXREG =“10000000” (128) . . . 57
4.7 DC level resulted by sine wave stop . . . 58
4.8 Implemented filter schematic for channel–0 . . . 58
4.9 Normalized polynomial Chebyshev–I coefficients table . . . 60
4.10 N –odd ladder topology for the Chebyshev–I filter . . . 60
4.11 Schematic capture for filter simulation . . . 62
4.12 Passive filter section response simulation . . . 62
4.13 Complete filter response simulation . . . 63
4.14 EL2090C non–inverting power amplifier schematic . . . 65
4.15 PC layout module for channel–0 (top view) . . . 66
4.16 Prototype module for channel–0 . . . 66
4.17 PC layout module for channel–1 (top view) . . . 67
4.18 Prototype module for channel–1 . . . 67
5.1 Prototype system in operation . . . 69
5.2 Implemented entity in FPGA (ASIC equivalent I/O ports) . . . 70
5.3 Graphical representation of FPGA usage . . . 70
5.4 MATLAB simulation for a 1MHz signal . . . 74
5.5 MATLAB simulation for a 5MHz signal . . . 74
5.6 Channel–0 reference voltage . . . 75
5.7 Channel–1 reference voltage . . . 75
5.8 Synthesized 1MHz signal (9.9VP P & 22VP P) . . . 76
5.9 Synthesized 5MHz signal (10VP P & 10.1VP P) . . . 76
5.10 System spectrum measurement . . . 77
5.11 System frequency response . . . 79
5.12 Normalized frequency response . . . 79
5.13 Spectrum for a 1MHz signal . . . 80
5.14 Spectrum for a 5MHz signal . . . 80
5.15 Spectrum for a 8MHz signal . . . 80
5.16 Dual channel 1MHz & 5MHz signal . . . 81
5.17 Independent frequency & amplitude operation . . . 81
6.1 Software prototype for sine waves control . . . 84
6.2 Ball grid array FPGA . . . 85
6.3 Proposed prototype for USB system communication . . . 85
Ω
Chapter 1 Introduction
This thesis presents the design and development of a novel programmable multichan- nel sine wave generator for a C–MEMS dielectrophoretic filter, intended to work as an automated research tool for bio–particle separation automation. It consists of independent frequency generators, using the direct digital frequency synthesis tech- nique. A FPGA chip is used to synthesize sine waves, programmed through a RS–232 to SPI interface of a personal computer. A prototype consisting of two channels is implemented developing two external modules from FPGA, in order to polarize the electrode arrays.
1.1 Dielectrophoresis
The dielectrophoresis phenomena (also known as DEP) is the translational motion of polar particles (induction of a force) due to polarization in a non–uniform elec- tric field, as seen in figure 1.1 [1]. It was first observed by Pohl in 1951, reporting his observations in several papers and a book [2]. Pohl called this phenomena as dielectrophoresis from the greek root phoresis (related to force) and dielectro by it’s electric origin. In the beginning it was believed that micro & nanoparticles may not be separated by DEP because they would require extremely high voltages. However, modern technology has made possible the fabrication of micro–electrode structures capable of producing DEP forces enough to overcome competing forces [1]. Thus, dielectrophoresis is now being used to concentrate, separate, and identify biological particles.
1.2 Problem Definition
Development of a low cost bio–particle separation is been investigated by ITESM–Mty and UCI as mentioned previously, alternative to common separation techniques like FACS (Fluorescent Activated Cell Sorting) and MACS (Magnetically Actuated Cell Sorting) techniques, discriminating the bio–particles by dielectrophoresis, referring to the use of electric fields optimized in frequency and magnitude, based only in particles
1. Introduction 1.2. Problem Definition
Figure 1.1: Particle in a non–uniform electric field
physical characteristics. Bio–particle separation requires several electrode arrays, excited by different optimized signals, and it is achieved by sequentially releasing and collecting previous particles from the electrode arrays. In figure 1.2 is illustrated the device concept [3].
Initial research process started the electrode arrays excitation using several com- mercial sine wave function generators, and signal adjustment (frequency tunning and amplitude control) is done “by hand”, one at time. Thus, an automated system is proposed for electrode arrays excitation, capable of creating the optimized signals for bio–particle separation, controlled by a single personal computer.
Figure 1.2: Schematic drawing of multistage CarbonDEP system
1. Introduction 1.3. Objectives
Figure 1.3: Multistage dielectrophoresis filter device
1.3 Objectives
1.3.1 General Objective
Design and implement a multiple–channel sine wave generator, independently pro- grammable in frequency and amplitude from a personal computer, for electrode arrays excitation automation.
1.3.2 Particular Objectives
• Implement a novel multichannel sine wave generator tool for bio–particle sepa- ration applications.
• Design a prototype capable of generating up to four independent sine wave signals.
• Achieve sine wave frequencies in a range from 800Hz up to 8MHz.
• Achieve sine wave amplitudes up to 20VP P.
• Obtain at least a SNR of 50dB.
• Configure the sine wave parameters using a personal computer.
• Construct at least one discrete generator for system testing purposes.
1. Introduction 1.4. Hypothesis
1.4 Hypothesis
A programmable multiple channel sine wave generator may be implemented based on a digital approach, so sine waves may be digitally created and controlled, making a latter conversion to analog sinusoidal forms. Voltage amplitude might be established by a controllable reference voltage, driven by digital logic either.
1.5 Justification
The goal of this work is the fabrication of a prototype capable for generating multiple sine wave signals, featuring signal creation, conditioning and control, complemented with a DEP platform stage. Thus, such a robust electronic system will greatly increase the portability of a self-contained DEP platform toward its displacement from labo- ratory to point–of–care locations. Moreover, since the system will be programmable, it will be capable of implementing a wide range of protocols for different bio–particle separation, and could represent a cost–effective option to hospitals, laboratories and individuals related to health care.
1.6 Contribution
Several papers covers techniques to improve digital sine wave generation, related to the fidelity output spectrum, memory compression techniques and to digital frequency tunning. However, they include a single generator without amplitude control [4, 5, 7, 11, 12, 13, 14, 15, 16]. Thus, we propose a multiple independent channel sine wave generator, featuring digital programmability in frequency and amplitude using a personal computer.
1.7 Document Organization
This thesis is organized in six chapters that are described as follows: Chapter 2 presents the Direct Digital Frequency Synthesis (DDFS), explaining with examples since the basic topology, covering to the complete topology, and how sine wave might be created from an ideal generator to a realizable generator. Chapter 3 describes the complete implementation of the generator’s digital stage, covering the programming interface from a personal computer using a RS–232 port, the RS–232 to SPI protocol conversion done in a microcontroller, and the FPGA logic stages related to the SPI programming interface, the DDFS engine and the look–up table memory. Chapter 4 discusses the complete generator’s analog stage, covering the digital to analog conver- sion, the amplitude controller conversion, the pre–amplifier with anti–aliasing filtering block, and the output power amplifier. Chapter 5 illustrates the most important tests for the system prototype and their corresponding results. Finally Chapter 6 presents the conclusions of this work, including some important recommendations for future work.
Chapter 2
Direct Digital Frequency Synthesis
2.1 Introduction
Direct digital frequency synthesis, also known as DDFS or simply DDS, consists of generating waveforms “piece-by-piece” [6], using a single frequency as a reference to establish a stable sampling time for the signal reconstruction [7]. Some of the DDFS architecture advantages are [8, 9]:
• Tuning capability from µHz and sub–degree phase.
• Extremely fast tuning output frequency (only one sample period).
• Eliminates manual system tuning.
• Not affected by components aging and temperature drift.
• Digital interface facilitates communication with microprocessors or microcon- trollers.
• Implementation is always stable. There is no need for an automatic gain control.
• Phase continuity is preserved over any frequency change.
The possible generated waveform may be any arbitrary periodic function, includ- ing –but not limited to– sine, saw-tooth, triangle or square waveforms [10].
This technique was first introduced by Tierney, Rader & Gold in 1971 [7], and it has been adopted in new system designs [9]. This chapter presents and examines the DDFS characteristics.
2. Direct Digital Frequency Synthesis 2.2. Basic DDFS Form
2.2 Basic DDFS Form
Figure 2.1 shows the basic DDFS implementation using a binary counter (address counter), a look up table (LUT) with a desired sampled wave (which may be imple- mented in ROM), a data register and a digital to analog converter (DAC) [8].
Figure 2.1: Simple form of a direct digital synthesizer
The binary counter receives a reference clock, fc, which is incremented by one with each cycle. According to the output value of the binary counter, it addresses a particular ROM location. For the sine wave case, this ROM must have stored a complete period; which means an equivalent sine amplitude of a complete cycle.
This information is then transfered to a data register that presents synchronously the digital amplitude values to a fast DAC [8]. Finally1, the DAC generates an electrical analog representation of the digital data, reconstructing the sine wave frequency fout. Now, the output frequency on this topology is determined by:
1. The frequency of the reference clock fc.
2. The number of bits, N, used in the address counter.
This is given by:
fout = fc
2N (2.1)
So, the output frequency fout can only be changed by modifying the speed of the reference clock, fc, or by incrementing/decrementing the number of samples in the ROM (the length of the address counter). Even though the AC performance and the analog fidelity is good enough [8], it is unpractical for a wide range of frequency values.
1The output must be also filtered to remove aliases frequencies.
2. Direct Digital Frequency Synthesis 2.3. Complete DDFS Form
2.3 Complete DDFS Form
To solve the problem of the complicated change of output frequency with respect to the reference, the system is modified using the scheme shown in figure 2.2.
Figure 2.2: Complete form of a direct digital synthesizer
By replacing the address counter by the phase accumulator produces a numerically controlled oscillator. The phase accumulator makes the function of a modulus M counter [8] that increments itself by M units with each cycle of the reference clock fc, where the M value is established by the tuning word. Now, the output frequency fout is determined by [10]:
fout = Mfc
2N (2.2)
Here:
• fout is the output frequency.
• M is the binary tuning word.
• fc is the reference –system– clock.
• N is the number of bits in the phase accumulator.
Equation 2.2 is the basic equation of any DDFS system [9].
It can be easily seen that parameter M allows the real–time varying of frequency, without changing the system clock and/or the number of bits in the accumulator. M is in fact the main input for the system. Every time the phase accumulator reaches it’s top value, it restarts again. If the M value is small, the phase accumulator will take several steps to complete the full counting and restart it; in the other hand, if the M value is big, the phase accumulator will take less cycles to complete and start again. This may be observed in figure 2.3, where a 4–bit accumulator has been simulated in MATLAB for M = 1 and M = 3.
2. Direct Digital Frequency Synthesis 2.3. Complete DDFS Form
0 5 10 15 20 25 30
0 5 10 15
Clock cycles
Phase accumulator value
A) 4−bit Phase accumulator behavior with M = 1
0 5 10 15 20 25 30
0 5 10 15
Clock cycles
Phase accumulator value
B) 4−bit Phase accumulator behavior with M = 3
Figure 2.3: Phase accumulator behavior with 4 bit resolution for M = 1 and M = 3
As shown in figure 2.3, the inherent behavior of the phase accumulator is that it acts as a digital positive slope sawtooth wave generator or a ramp [10], without requiring either a ROM or LUT. Note when the M value is a power of two – i.e.:
M = 1 (20) – the counter returns to zero, or to the same phase value with each overflow. Instead, if M is not a power of two – i.e.: M = 3 – the counter does not returns to zero or to the same previous phase with every overflow, and it requires several overflows to get there [11].
2. Direct Digital Frequency Synthesis 2.4. Sine Wave Generation
2.4 Sine Wave Generation
As mentioned before, the DDFS architecture generates a sawtooth wave by itself, and it could generate any kind of periodical signal. For the specific case of a sine wave, a
“translation” [10] must be accomplished after the phase accumulator.
A continuous–time analog implementation of a sine wave presents a complete periodic angular phase range from 0 to 2π, so the digital scheme must do the same.
Consider the sine wave oscillation as a vector rotating around a circle, as shown in figure 2.4. In a DDFS architecture, the phase accumulator is the one who moves that vector, and acts as a phase wheel [10]. In this case, a 4-bit accumulator is being used.
Figure 2.4: A digital phase wheel with 4 bit resolution
Every point over the phase wheel corresponds to an equivalent point on the sine wave cycle. It may be observed that as the vector rotates around the wheel, the sine of the angle generates a corresponding waveform. One revolution of the vector at a constant angular speed – determined by the M factor and the system clock fc – will create a complete cycle of the sinewave. The phase accumulator provides the equally spaced angular increment for the vector’s linear rotation. This could be appreciated in figures 2.5 and 2.6, where a simulation of the expected output2 of the DDFS architecture is presented for a 4–bit resolution accumulator with M = 1 and M = 3.
2The quantized levels of data stored in ROM have not been considered, it assumes exact values.
2. Direct Digital Frequency Synthesis 2.4. Sine Wave Generation
0 5 10 15 20 25 30
0 5 10 15
Clock cycles
Phase acc. value
A) 4−bit Phase accumulator behavior with M = 1
0 5 10 15 20 25 30
−1 0 1
Clock cycles
Normalized ROM output
B) Normalized ideal ROM output for a 4−bit phase accumulator with M = 1
Figure 2.5: Transfer from a digital phase with 4 bit resolution to a sine wave with M=1
0 5 10 15 20 25 30
0 5 10 15
Clock cycles
Phase acc. value
A) 4−bit Phase accumulator behavior with M = 3
0 5 10 15 20 25 30
−1 0 1
Clock cycles
Normalized ROM output
B) Normalized ideal ROM output for a 4−bit phase accumulator with M = 3
Figure 2.6: Transfer from a digital phase with 4 bit resolution to a sine wave with M=3
2. Direct Digital Frequency Synthesis 2.4. Sine Wave Generation
The amount of points over the phase wheel will be determined by the number of N –bits in the phase accumulator. In table 2.1 are presented some common values used for the number of points over the phase wheel, in function of the length of the accumulator. For example, referring to table 2.1, for a 20–bit accumulator, the phase wheel will be divided in 1’048,576 equally distanced points.
Table 2.1: Number of points for N –bits (2N) N –bits Number of points (2N)
4 16
6 64
8 256
10 1,024
12 4,096
14 16,384
16 65,536
18 262,144
20 1’048,576
22 4’194,304
24 16’777,216
26 67’108,864
28 268’435,456
30 1,073’741,824 32 4,294’967,296 40 1’099,511’627,776 48 281’474,976’710,656
In case of M = 1, the increment on the phase wheel will be the unit, and it will conform the slowest frequency achievable by the architecture [9]. So, this will be the minimum frequency or frequency resolution, and is defined by3:
fmin = fc
2N (2.3)
Thus, the designer is able to choose the length in N –bits of the phase accumulator considering the system clock frequency, to get a desired frequency resolution [9].
Now, the maximum frequency reachable by the architecture is established by the Nyquist sampling theorem, and it is:
fmax = fc
2 (2.4)
3Equivalent to system without phase accumulator, as seen in equation 2.1
2. Direct Digital Frequency Synthesis 2.4. Sine Wave Generation
However, for practical applications, the maximum output frequency is limited to one half of the Nyquist rate as follows [6, 7, 8, 9, 10]:
fmax = fc
4 (2.5)
This limitation of fc/4 over the output frequency allows a flexible transition from fc/4 to 3fc/4 over the output low–pass filter [7]. Then, the DDFS smoothing filter response must be as shown in figure 2.7.
Figure 2.7: Proposed filter response for a DDFS output
2. Direct Digital Frequency Synthesis 2.5. Phase Quantization
2.5 Phase Quantization
As seen previously, the phase of the sinusoidal wave is encoded in the accumulator, defined by the N –bit length. So, for an N –bit accumulator, there must be 2N ROM addresses or entries [9]. Assuming that one byte is enough to define the output DAC amplitude, to convert a 32 bit phase wheel we require 232 ROM addresses (4GBytes) as shown in table 2.1. Of course, this illustrates a non–practical implementation [8].
A better approach is to truncate the phase of the wheel to the most significant bits, and discard the lowest bits for a practical implementation. Thus, in the case of the 32–bit phase wheel, it may be considered to use the most significant bits, i.e. 12 bits, which leads to a ROM size of 4KB, and truncate or ignore the lower 20 bits [8]. This solution leads to a sine wave in which not all the phases of the wheel are completely defined. However, the internal angular resolution is still present. Figure 2.8 shows an output example of a non–truncated wheel, where all clock cycles have assigned an amplitude, and the output achieved by phase truncation, where the clocks cycles not having a corresponding amplitude value, preserves their previous value. Note that the desired frequency is still able to be synthesized. The phase truncating process may be implemented as illustrated in figure 2.9.
Figure 2.8: Sine wave generated by a non truncated & truncated phase wheel
For example, considering the wheel shown in figure 2.10, a 6 bit phase accumulator is implemented, subdividing the circle by 26 = 64 equally spaced points, or 360◦/64 = 5.625◦. However, the phase is truncated to a 4–bit wheel, so the resolution presented to DAC will be 24 = 16 points, or 360◦/16 = 22.5◦. Then, an increment of M = 3 is used to rotate the vector, so the phase accumulator increases on each clock cycle by a
2. Direct Digital Frequency Synthesis 2.5. Phase Quantization
Figure 2.9: DDFS System with phase truncation from N to N − P bits
factor of 3. For the first cycle it gets a value of 3, but the phase is truncated by 2 bits and the output phase is divided by four, so the output phase will be 0.75. Finally the phase value is truncated in the non–integer part, so the phase “0” is computed. For the second cycle, the phase accumulator has a value of 6, so the output phase will be determined to 6/4 = 1.5. Again, the non–integer part is discarded and the output phase is truncated to “1”. For the third cycle, the phase accumulator has a value of 9, and the output phase is 9/4 = 2.25, truncating yields to “2”, and so on. Table 2.2 shows this process from cycles 0 to 5.
Figure 2.10: Phase wheel (with 6 bit resolution) truncated to 4 bit with M=3
For further comprehension, a complete and exhaustive simulation4 was performed
4The quantized levels of ROM data are not considered yet.
2. Direct Digital Frequency Synthesis 2.5. Phase Quantization
Table 2.2: Truncated 6-bit to 4-bit wheel output with M = 3
with MATLAB, showing the output of the original 6-bit phase and the output achieved for a 2 bit truncation. Figure 2.11 illustrates the simulated outputs of this example.
Non-truncated 6-bit phase wheel with M = 3
Clock cycles (T)
6-bit Phase wheel truncated to 4-bit with M = 3
Figure 2.11: Simulated outputs for non-truncated & truncated phase wheel with M = 3 Clock cycles (T)
Clock cycle T
Original Rotation Ф = Δ Фo/64
Truncated Rotation Ф = ΔФ T/l6
0 0 0.00° 0 0.00°
1 3 16.87° 0 0.00°
2 6 33.75° 1 22.50°
3 9 50.62° 2 45.00°
4 12 67.50° 3 67.50°
5 15 84.37° 3 67.50°
2. Direct Digital Frequency Synthesis 2.6. Amplitude Quantization
2.6 Amplitude Quantization
Once the phase accumulator has been considered as the address pointer to the mem¬
ory, the corresponding discrete sine amplitude to phase relation is established as shown in figure 2.12.
Figure 2.12: Relation from a phase angle φT to an amplitude value A[φT]
The number of bits n for amplitude resolution is independent of phase accumulator length. The size of the storage ROM must be ( 2Q x n) [12]. Then, the needed data to be stored in memory may be determined by:
Here:
• A[φT] is the digital sine wave amplitude for a discrete angle φT.
• n is the number of bits used to define the resolution of the wave amplitude.
• Q is the truncated length of bits used to define the phase resolution.
• φT is the discrete angle in which φT is an integer Є [0,1, 2 , . . . , 2Q — 1].
or
2. Direct Digital Frequency Synthesis 2.6. Amplitude Quantization
This is the most direct way to generate the sinusoidal wave. To illustrate the concept, in table 2.3 is shown the calculated data from equation 2.7 using an 8–bit length for the amplitude resolution (28 = 256 levels), and a truncated phase resolution of 4–bit (24 = 16 angles), obtained from the MATLAB simulation shown in figure 2.13. In this case a ROM of with a 16–bytes capacity will be required.
Table 2.3: Computed sine wave for n = 8 & Q = 4 φT Angle Sine A[φT]
0 0.0◦ 0.0000 127 1 22.5◦ 0.3826 176 2 45.0◦ 0.7071 217 3 67.5◦ 0.9238 245 4 90.0◦ 1.0000 255 5 112.5◦ 0.9238 245 6 135.0◦ 0.7071 217 7 157.5◦ 0.3826 176 8 180.0◦ 0.0000 127 9 202.5◦ –0.3826 78 10 225.0◦ –0.7071 37 11 247.5◦ –0.9238 9 12 270.0◦ –1.0000 0 13 292.5◦ –0.9238 9 14 315.0◦ –0.7071 37 15 337.5◦ –0.3826 78
0 5 10 15
0 50 100 150 200 250 300
Quantized sine wave generated for n = 8 & Q = 4
Phase (φT) Amplitude A[φ T]
Figure 2.13: MATLAB simulation for a quantized sine wave with n = 8 & Q = 4
2. Direct Digital Frequency Synthesis 2.7. Data Compression
2.7 Data Compression
Instead of storing the entire sine wave f (φ) = sin(φ) for 0 ≤ φ ≤ 2π, the sine wave symmetry allows us to reduce the ROM size [9]. However, the decrease in look–
up table capacity leads to an increase of additional logic [9][12]. Two approaches are commonly used: the half sine symmetry & the quarter sine symmetry. These two techniques needs a rotation of the phase wheel by an offset of 1/2–LSB (lowest significant bit) – reflected on an phase offset of ∆φ/2 – to get a proper symmetrical sine wave in the synthesis [12]. This modification is illustrated in figure 2.14.
Figure 2.14: Rotation over the phase wheel to explode symmetry
This offset does not affect the sine wave output, as seen in figure 2.15, where a MATLAB simulation is shown for a rotated wheel with n = 8 and Q = 4.
0 5 10 15
0 50 100 150 200 250 300
Rotated sine wave generated for n = 8 & Q = 4
Phase (φT) Amplitude A[φ T]
Figure 2.15: MATLAB simulation for a rotated sine wave with n = 8 & Q = 4
2. Direct Digital Frequency Synthesis 2.7. Data Compression
Thus, for a complete phase wheel, the required data to be stored in memory must be determined adding this offset to equation 2.7, leading to:
2.7.1 One Half Sine Symmetry
The one half sine wave symmetry is the easiest way to reduce the memory require
ments. It takes advantage of the MSB (most significant bit) of the truncated phase accumulator to differentiate one half of the sine wave from the other half. Thus, the new required space is reduced from ( 2Q x n) to ( 2Q - 1 x n). This implementation must consider starting the half sine wave from an angle of ̶π/2 to + π / 2 as shown in figure 2.16.
Here, the MSB determines the reading direction over the ROM addresses. So, when the M S B = 0 the ROM will be read forward, and when the MSB = 1 the R O M will be read backward. This technique converts the inherent sawtooth wave form from the phase accumulator to a triangular wave form. To illustrate the concept, a M A T L A B simulation has been done considering the half sine wave for −π/2 ≤ φ ≤ π/2. In table 2.4 is shown the computed data. Note that the MSB has been separated in the binary addresses for clarity. The conformed wave form generated by data shown in table 2.4 is shown in figure 2.17, where the change from sawtooth form to triangular form could be appreciated.
2. Direct Digital Frequency Synthesis 2.7. Data Compression
Table 2.4: Half sinusoidal wave for n = 8 & Q = 4 φT Binary φT Angle Sine A[φT]
0 0–000 −78.75◦ –0.9807 2
1 0–001 −56.25◦ –0.8314 21
2 0–010 −33.75◦ –0.5555 56
3 0–011 −11.25◦ –0.1950 102
4 0–100 11.25◦ 0.1950 152
5 0–101 33.75◦ 0.5555 198
6 0–110 56.25◦ 0.8314 233
7 0–111 78.75◦ 0.9807 252
8 1–000 101.25◦ 0.9807 252
9 1–001 123.75◦ 0.8314 233
10 1–010 146.25◦ 0.5555 198 11 1–011 168.75◦ 0.1950 152 12 1–100 −168.75◦ –0.1950 102 13 1–101 −146.25◦ –0.5555 56 14 1–110 −123.75◦ –0.8314 21 15 1–111 −101.25◦ –0.9807 2
0 5 10 15 20 25 30
0 5 10 15
Truncated 24 (16) length phase from phase accumulator
Clock cycles (T) Phase φ T
0 5 10 15 20 25 30
0 5
Modified 23 (8) length phase (half inverted)
Clock cycles (T)
ROM address
0 5 10 15 20 25 30
0 100 200
Reconstructed sinusoidal wave using half symmetry
Clock cycles (T) Amplitude A[φ T]
Figure 2.17: Sinusoidal wave with n = 8 & Q = 4 using half symmetry
2. Direct Digital Frequency Synthesis 2.7. Data Compression
2.7.2 One Quarter Sine Symmetry
The most common compression technique used to reduce the size of the look–up table, is to store only π/2 radians of the sine wave information [12]. This is accomplished following the scheme shown in figure 2.18.
Figure 2.18: Block diagram of the one quarter symmetry method
Here, the two most significant bits from the phase accumulator are used to decode the quadrant, while the remaining Q − 2 are used to address the 0 ≤ φ ≤ π/2 look–
up table. The most significant bit establishes the sign of the output signal, while the second most significant bit determines if the ROM addresses are read upward or downward. The phase accumulator is used “as is” [12] for the first and the third quadrant, while in the second and fourth the phase bits must be complemented (in- verted), so the slope could be changed. As shown in the output from the ROM in figure 2.18, the signal corresponds to a full rectified version of the sine wave, while in the output of the second complementor [12], the signal is multiplied by −1 in the phase over π ≤ φ ≤ 2π.
The complementors in the system are simple 1’ complementors, so they might be constructed using controlled exclusive or (XOR) gates [13][14]. Then, with the inclusion of this additional logic, the approach achieves the use of only 2Q−2 ROM entries as shown in figure 2.18, leading to a LUT–size compression ratio of 4:1 [9].
There are several other techniques to achieve the reduction in memory require- ments. Another one uses the sine/cosine symmetry, based on the fact that the sine wave from π/2 to π is the same as the cosine from 0 to π/2. This means that only 1/8 of the sine & cosine functions are stored in ROM [15]. Another designs have got compression ratios from 11:1 [6] to even 165:1 [9] employing first–order Taylor series expansion.
2. Direct Digital Frequency Synthesis 2.7. Data Compression
Ω
Chapter 3
Digital Stage Implementation
3.1 Introduction
The current implemented multichannel frequency generator, was implemented using the Direct Digital Frequency Synthesizer architecture, presented in last chapter. It has been developed to assist as a research tool to help in the investigation of the Dielectrophoresis (DEP) phenomenon, realized between the Instituto Tecnol´ogico y de Estudios Superiores de Monterrey, Campus Monterrey and the University of Cal- ifornia, Irvine in the last years. In figure 3.1 is shown a pictorial block diagram of the complete research line followed by both institutions. The intended place of this work in the research path is illustrated inside the dashed line in figure 3.1.
Figure 3.1: Methodology for the DEP research
3. Digital Stage Implementation 3.1. Introduction
The multichannel frequency generator consists of two independent sine wave fre- quency generator channels, which can be programmed from a personal computer in a frequency range from 60Hz to almost 12.5MHz and in amplitude range from 1.7VP P
to 22VP P each one. Even though just two channels are implemented, the design was done to support four independent channels. The full design implementation includes the software that communicates from the personal computer (PC) by an adjusted data protocol, a digital stage implementation built over programmable logic, using a Microcontroller (µC) and a Field Gate Programmable Array (FPGA), and the analog module to conform the final signal. Therefore, the prototype description is divided according to the nature of the subsystems in two stages, as seen in the block diagram presented in figure 3.2. The main stages are:
1. Digital Stage Implementation. It covers from the definition of the com- munication’s protocol & communications modules, through the main DDFS generators of both channels, and decoding of compressed ROM data.
2. Analog Stage Implementation. It covers from Digital to Analog conversion of the signal’s frequency and the signal’s amplitude to a current signal, the Current to Voltage conversion, filtering and final power amplifying.
Figure 3.2: Block diagram of the complete prototype
Figure 3.3 shows a picture of the complete implemented multichannel sine wave generator.
3. Digital Stage Implementation 3.1. Introduction
This chapter focuses in the Digital Stage Implementation, which is described and examined. Figure 3.4 shows the digital boards of the prototype.
Figure 3.3: Complete multichannel sine wave generator
Figure 3.4: Digital boards corresponding to the working prototype
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
3.2 Data Transfer (RS232–SPI)
In 2006 was developed an implementation of the DDFS architecture using an FPGA chip [16]. It was built in a Pegasus Development Board from Digilent Inc., with aR Spartan–2 XC2S50 FPGA from Xilinx . It used the on–board eight slide switchesR to load an 8–bit programming word as the tuning parameter M, so an 8–bit phase accumulator was used. The phase accumulator was truncated to a 5–bit phase wheel, leading to a phase ROM definition of 360◦/25 = 11.25◦. The system worked with a pre–scaled frequency clock from 50MHz to almost 20KHz. This design was primarily oriented to the study of the effects in phase truncation, but is not appropriate for a wide range frequency tuning, because of the slow frequency system clock, the limited length of the phase accumulator and tuning word, and moreover, the frequency tuning was done “by hand”. So, for a PC–controlled, wide–range frequency system another solution must be employed, and it requires a serial load stage instead of a parallel way.
One of the most common ways to send information from a personal computer to an electronic system is using the serial port based in the RS–232 [17] standard. Even though modern computers are not supporting this communications port anymore – which has been replaced by the Universal Serial Bus (USB) –, it is easy to get an adapter to employ the USB port as an RS–232 port, and the programming for sending data over this port is quite flexible, depending on the used development software (C/C++, VisualC#, MATLAB, etc). Some of the RS–232 characteristics are [17]:
• Works in asynchronous mode.
• Can receive and transmit.
• May work in full–duplex asynchronous operation.
• Needs a driver for level shifting.
Now, the RS–232 port is mostly a personal computer–oriented port. Electronic devices which can be programmed in a serial mode, usually employs another serial protocol modes, including the Inter–Integrated Circuit (I2C) protocol, and the Serial Peripheral Interface (SPI) protocol. The SPI standard is an effective and simple way to communicate two or more electronic devices, which have some of the following characteristics [18]:
• Used to facilitate and to speed up of moving data between devices.
• Works in synchronous mode.
• Works in Master–Slave configuration.
• Allows data exchange.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
3.2.1 Programming Word Format
To establish the communication data format provided from the PC to the system, the design parameters must be set first, in order to match what computer may send, and what the system may receive. Because of this work nature, it must consider three special sections:
1. The most important input for any DDFS system: the M parameter, based on the N –length of the phase accumulator.
2. As this system must conform a programmable amplitude signal either, the volt- age amplitude parameter must be set in the programming word.
3. Finally, the system must generate independent frequency signals, so there must be a way to select a particular channel.
So, according with these considerations, the next values are proposed:
1. A 24–bit length phase accumulator (one for each channel).
2. An 8–bit length amplitude control (per channel).
3. A design with four independent channels, selected by 2–bit.
So the serial programming word must have at least 34–bit. However, referring to equation 2.5, at most one quarter of the maximum frequency should be synthesized, which means that only a quarter of the M parameter is used. Then, the M value could be truncated to 22–bit, eliminating the 2 MSB bits. Thus, the serial programming word was set in 32–bit. According to this, the programming word format may be subdivided into eight hexadecimal values, and it was established as shown in figure 3.5.
Figure 3.5: Proposed programming word format
Where:
1. Bit[7..0] Establishes the voltage amplitude.
2. Bit[29..8] Establishes the M parameter.
3. Bit[31:30] Selects the desired channel.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
3.2.2 Data Protocol Adjustment
Initially, the tests for sending data to the system were done using a generic serial port terminal named RealTerm Serial Capture Program 2.0.0.57 [19]. To be “accessi- ble” in this tests, the ASCII (American Standard Code for Information Interchange) equivalent characters1 were chosen instead of “real” hexadecimal values.
For example, if an hexadecimal value of 0xF is required to be sent, in the terminal must be typed the ASCII letter “F” (equivalent to a real 0x46 hexadecimal value).
Using this approach, the complete word format needs to be sent to the system with a “null character” termination, so the system could determines that all word has arrived. This null character was proposed to be the ASCII character “H”. In table 3.1 is shown the complete equivalent values for the typed characters and their real hexadecimal values [20].
Table 3.1: Equivalent ASCII characters hexadecimal values ASCII Character Hexadecimal Value
“0” 0x30
“1” 0x31
“2” 0x32
“3” 0x33
“4” 0x34
“5” 0x35
“6” 0x36
“7” 0x37
“8” 0x38
“9” 0x39
“A” 0x41
“B” 0x42
“C” 0x43
“D” 0x44
“E” 0x45
“F” 0x46
“H” 0x48
For example, and referring to table 3.1, if an hexadecimal programming word of 0x1234ABCD is required to be loaded at the system, in terminal must be written2
“1234ABCDH” (without quotes), and the system will receive the hexadecimal value of 0x313233344142434448. This information is sent from the terminal across a serial COMx port, thus, it cames out from the PC in RS–232 format.
1In case of non–numerical characters, only capital letters are allowed.
2Note the final “H” character.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
As mentioned before, the most appropriate serial protocols for a system intended to be packed into a chip are the I2C or the SPI protocols. For this system, the SPI protocol was chosen, then a translation must be accomplished between both devices:
the computer that sends data in RS–232 format & the frequency generator that must receive data in SPI format; so an intermediate module is present. This one was built using a microcontroller PIC18LF2525 [21] from Microchip . The translation doneR by this module may be appreciated in the flow chart shown in figure 3.6.
Figure 3.6: Flow chart for the RS232–SPI conversion
The reasons that were considered to choose the use of the SPI protocol in the frequency generator more adequate than implementing directly the RS–232 are:
• RS–232 is an asynchronous protocol that must run over a fixed standard speed in both terminals (PC & generator).
• The RS–232 speed depends directly on the main clock frequency, so if this is changed, the RS–232 speed will change too and it won’t synchronize with PC.
• SPI is a synchronous protocol that requires its own external clock to receive &
send data, so it is independent of the main clock frequency.
• The SPI implementation in the generator is easy to achieve.
• The SPI protocol allows the generator to be driven by any embedded system.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
In order to establish the translation between the RS–232 & SPI, another consider- ation must be noted. In the format that RealTerm sends data, each ASCII character uses one byte, then the total information length is eight bytes3. However, the sys- tem must receive four bytes, so a conversion from ASCII characters to an equivalent hexadecimal value is needed.
Since each hexadecimal value requires 4 bits, the other 4 bits on each byte must be discarded. This is done by the function named “CONVERT ASCII TO HEX ” in figure 3.6, and is detailed in the “a)” flow chart shown in figure 3.7. The numerical characters (0...9) are converted using a 0x0F (00001111) mask with a logical AND operation. The non–numerical characters (A...F) receives an offset of nine in their values before the AND function.
Figure 3.7: Flow charts for a) ASCII to Hex Conversion b) Nibbles swapping & mixing
Once done, this equivalent hexadecimal values are then packed in pairs. According to their order position (starting in position zero): the even nibbles are swapped into the high nibble, and the odd nibbles remains in the low nibble. The high and the low nibble for each byte are then mixed by the use of a logical OR operation. This procedure refers to function named “MIX 8 NIBBLES INTO 4 BYTES ” shown in figure 3.6, and is detailed in the flow chart “b)” presented in figure 3.7. At the end of this procedure, data is ready to be sent to the frequency generator.
3The “null character” is not considered here, given that it is not received by the generator.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
3.2.3 Microcontroller to FPGA Interface
The complete algorithm is programmed in the microcontroller using assembly lan- guage4, and is implemented following the schematic shown in figure 3.8. All schemat- ics related to external hardware (µC interface & the Analog Modules presented in next chapter) as well as their layouts were done using the Freeware Windows version ofR the Cadsoft EAGLE Layout Editor Ver. 4.16r2 [22].
Figure 3.8: Microcontroller interface schematic
The most important established parameters in microcontroller are: The USART (RS–232) speed (or baudrate), and the SPI baudrate & waveform setting. The pro- posed configuration for the RS–232 port (in PC & µC) is: 9600 bits per second (bps), 8–data bits, no parity and one stop–bit (9600, 8–N–1). Considering that the µC is running with a crystal oscillator of 4MHz, then the USART speed parameter n is determined by [21]:
9600bps = 4 × 106Hz
16 × (n + 1) (3.1)
n = 4 × 106Hz
16 × 9600 − 1 ⇒ 25 (3.2)
The waveform setting for the SPI transfer was the “[1,1]” standard mode [21], and the lowest speed was chosen in the µC SPI–module. So, the baudrate is determined by [21]:
SP Ibaudrate = Fosc
64 = 4 × 106Hz
64 = 62, 500bps (3.3)
4Code is presented in the Appendix Codes & Circuits at the end of this document.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
Low speeds are used for easy hardware debugging purposes. These speeds may be increased to higher values considering that the RS–232 speed must be the same between PC & µC. However, the SPI baudrate does not presents any problem to make it faster.
As seen in figure 3.8, there are six lines (pins from 13 to 18) used in the interface.
The lines named RX and TX belong to the RS–232 section, and the lines named CS#, SCK, SDI & SDO belongs to the SPI section. Their functions in the system are shown in table 3.2.
Table 3.2: Functions of each pin in the µC
Pin name Function
TX Transmits RS–232 data from µC
RX Receives RS–232 data into µC
CS# Line used from µC to Select the FPGA Chip for SPI transfers SCK Master Serial Clock used to synchronize SPI data transfers
SDI Serial Data In. Receives data into µC in SPI format SDO Serial Data Out. Transmits data from µC in SPI format
These lines have been directed to an 8–pin ribbon connector, and its location in the designed printed circuit board (PCB) for this stage is marked under the square shown in figure 3.9. The pin order set in connector, and the advantage on it, will be discussed later in next subsection.
Figure 3.9: RS–232 to SPI data connector location
Pin number 12 in the µC is also used, and a LED is attached for debugging purposes and to monitor the SPI activity. Figure 3.10 shows the assembly guide of the designed µC module for this stage. µC board is used to hold the multiple voltages power supply either. In figure 3.11 is shown the prototype implemented for this system.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
For the power supply implementation, the voltage regulators LM7812 (IC5), LM7912 (IC6), and the 3.3V zener diodes D1 & D2 were replaced by single use of LM7815 &
LM7915 voltage regulators (diode places were bridged with wire).
Figure 3.10: PC layout of transceiver with multiple voltages power supply
Figure 3.11: Transceiver & power supply board
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
3.2.4 FPGA to Microcontroller Interface
All the digital logic related to the multichannel frequency generator is implemented in an FPGA chip, using a development board from SparkFun Electronics . It consists ofR a Spartan–3E XC3S500E–PQ208 from Xilinx with almost all the Input/OutputR (I/O) pins available to interconnect external custom peripherals. However, there are two implemented peripherals on board: an RS–232 level shifter MAX3232 from Maxim , and a non volatile 16–Mbit DataFlash AT45DB161D from AtmelR .R This development board is shown in figure 3.12.
Figure 3.12: Spartan–3E development board used for the generator
The included RS–232 level shifter is not routed directly to the FPGA. Instead, it has an 8–pin connector intended to route the level shifter (or driver ) via external jumpers. This characteristic gives the advantage to use the driver in an external module – like the RS–232 to SPI module seen previously – with the employment of a ribbon cable (or flat cable). The only requisite is to respect the pin order established in this connector, which may be appreciated in figure 3.13, extracted from the schematics provided by SparkFun [23]. It may be easily seen in figure 3.13 that signals named TXD & RXD are connected to pins 4 and 6 respectively. So, this setting was kept in the µC data connector. Odd pins on FPGA board are routed to generic FPGA I/O pins, so these were used to implement the SPI data transfer explained before.
According to figure 3.13, the pin configuration used to communicate the chain PC–
µC–FPGA as seen in figure 3.95, is shown in table 3.3.
5In figure 3.9 the connector’s pin enumeration is different, but pin order is still the same.
3. Digital Stage Implementation 3.2. Data Transfer (RS232–SPI)
Figure 3.13: RS–232 FPGA board connector configuration
Table 3.3: Assigned pin functions in µC board Pin Function Pin Function
1 SDO 2 Not connected
3 SDI 4 TX
5 SCK 6 RX
7 CS# 8 Not connected
Once these settings were established in the µC layout, both data connectors (from µC and from RS–232 FPGA board) might be connected with a ribbon cable as seen in figure 3.14. Note that pin number 1 – in both boards – is identified by the red wire in the flat cable.
Figure 3.14: Cable connection between µC & FPGA board
3. Digital Stage Implementation 3.3. SPI Load Module
3.3 SPI Load Module
As mentioned before, the µC was set with the “[1,1]” SPI standard waveform to make data transfers. This standard establishes that the information bit presented in the output serial path (SDO) must be defined before the low to high transition of the clock signal. In addition, when clock has no activity it must remain in a high logic level. In the SPI standard there is an input serial signal (in this case, into the µC), however, for this specific work it has not been used and it won’t be treated. Now, most of the integrated circuits with a selection line, intented to take their attention for processing (a chip select or CS), requires a “0” logic level to activate them. Then, this consideration was taken to load data to the frequency generator (N CS). So, the complete wave form data from the µC to the FPGA board will be as shown in figure 3.15 – adapted from µC datasheet [21] –.
Figure 3.15: SPI mode waveform from µC to FPGA board
As soon as information arrives to the FPGA, it must be converted inside to a parallel form. This must be accomplished by using cascaded flip–flops. The proposed flip–flops used here were “Data” flip–flops (or “D” flip–flops). Considering that the low to high transition in clock indicates data is ready, then the use of “D” flip–flops with positive slope load must be used. According to this, in figure 3.16 is shown the required topology for serial to parallel conversion [24], where SLI (serial input) receives data into FPGA from SDO of µC.
Figure 3.16: Serial to parallel conversion
3. Digital Stage Implementation 3.3. SPI Load Module
However, the data loading process must be done only when the FPGA is selected (N CS = 0), otherwise it must not respond to serial data. So, the truth tables shown in table 3.4 must be used to control the data flow to frequency generator.
Table 3.4: Truth tables for controlled serial loading
N CS SCK CLK N CS SDI SLI
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 0
1 1 0 1 1 0
According to data shown in table 3.4, the complete load stage was implemented as shown in diagram from figure 3.17.
Figure 3.17: Controlled serial to parallel conversion
Once the load and serial to parallel stages are set, the 32–bit programming word seen previously is ready to be used in the next sections. For convenience, the 32–bit serial to parallel converter (hence 32–bit shift register ) has been divided in 3 sections starting at the MSB: a 2–bit section (channel selector), a 22–bit section (M tuning value), and an 8–bit section (amplitude control), as seen in figure 3.18.
Figure 3.18: Block diagram for the shift register division
