Cambios realizados al plan de estudios

Figure 4 Simulated Waveform from SPICE

A second , more significant, effect was due to crossta l k , or cou p l i n g between t h e I i n cs To meet the capa c i tance budget, the original phys i ­ c a l design a i med t O m i n i m i ze t h e capac i tance ro

ground. An undesired result was that the m u tual capaci tance from l i ne tO l i ne, while sti l l smal l . beca me proporti o n a l ly la rge r, thus i ncreas i ng the cou pl ing from l i n e to l i n e . The vol tage on one l i ne was a ffected by vo l tages on ne a rby l i nes: transitions were aided by l i ke transit i ons and slowed by oppos ing trans i tions. In the worst cas e . the m a gn i tu d e of t h i s v a r i a t i on was as much as 24 nanoseconds.

This worst case occu rred on a group of l i n es i n close prox i m i ty to a " spare " l i n e , nor con­ nected or term i nated , which con tributed add i ­ tional mutual cap acitance , thus enhancing the cou p l i n g . This spare l i n e , i ncl uded to red uce the need for engi neering change orders to the b a c k p l a n e , n e a r l y n e e d e d a n E C O fo r i r s remova l , which could have d e layed several new prod u c ts . Howeve r , a t i m i ng a na l ysis sh owed that i ts re mova l was unnecessary . lt shou l d be emphasized that this efkn was nor visi ble u nr i l actual bus tra ffi c, consist ing of random data par­ terns, was being transferred on a large bus con­ figuration . Test patterns were too smal l and roo regu lar to show t hese sign i ficant effects

S i m u l t a n e o u s swi tc h i n g n o i s e , d e s c r i b e d above , was a l so i nvestiga ted lwcause i ts effect was simi lar ro the effect of crossta l k . Al l VAX I31

data signa ls except one were swi tched simu lta­ neous ly, and the induced voltage was mon i tored on th e rema i n i ng l i ne, w h i c h was fi xed i n the high (inactive driver) state . Ground pins were then broken off one at a t i m e , the voltage be ing

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m e asured aft e r the remova l of each p i n . As a resu l t the i n d u c e d vol tage i n c reased from an insignificant level with L .:; ground pins ro more than one volt w i t h on ly .1 ground pins rem a i n ­ i n g . Wit h o n e more p i n remove d , the c h i p n o lo nger passed s e l f-test . These resu lts s h owe d t hat only a few ground pins a re necessary for the c h i p to operate . but 1 5 are needed to preven t the ad d i t ion o f noise t o t h e hus .

The t i m i ng analysis i nvolved fabricating spe­ c i a l l o ts of 7 87 3 2 i n t e r face c h i p s w i t h t h e fastest and s lowest poss i b l e process variat ions . Fro m these lots c h i ps were se l ected at the abso­ lute specification l i m its. These chips were care­ fu l l y me asu red i n a ra n ge of c o n fi g u ra t i ons . i nc l u d i ng one beyond the speci fi ed l i m its. 'fhen r h e t i m i n g marg i ns were c a l c u l a ted over t h e speci fi ed range of opera t i ng conditions. W h e n a l l poss i b l e w o r s t - c ase c o n d i t i o ns a nd t h e effects descri bed above had been i ncluded, the c a l c u l a t e d t i m i n g m a rg i n was r e d u c e d to

0. 5 na nosl'conds . Design verification resting on this worst-casl' system showed that it cou ld sti l l operate a t a frequ ency I 0 percent higher than th at spe c i fied over the fu l l operating range o f temperature a n d voltage .

Summary

The VAXBI bus was desi gned to a rigorous bus­ archi tectu re speci ficat i o n . After m i no r adjust­ me nts during design veri fication testi ng, the hus met a I I rhe req ui rem enrs of t hat spe c i fi ca t i on . I n part i c u l ar, this testing proved that the YAXI3l

bus can operate i nde pendently of system config­ uration .

Severa l other points should be noted by bus designers for fu ture products :

1 . Design ing a prod uct to a rigorous spec i fi ­ cation, cal led top-down design , can rea l l y work .

2 . D i ffe rential signals arc recomme nded for cri tical t i m ing. They arc best l ocated on t h e s a m e p r i n t e d - c i r c u i t l a y e r o n a mod u l e .

3 . Test i n g s h o u l d be p e r for m e d o n r e a l hardware w i t h rea l data , a s close ly a s i t can be a pproxi mated d u r i n g the desig n process. Too often. the test patte rns run on test structures y i e l d n o t h i ng but rhe e x p ected resu l ts . Test i n g s h o u l d a lso reveal unexpected problems, not simply corroborate the design .

Digital Technical journal

4 . Ground rerum paths requ i re carefu l con­ sideration , particularly u nder cond itions of simu ltaneous switc hing .

Acknowledgments

The fol lowing peopl e were i nva l u able i n the su ccessful and t imely conclusion of the VA.XBI proj ect : Dana B l a n c ha rd . Fra n k B o m b a . Bob C h e n , Norm C o m m o , Ron D e s ha r n a i s , R i c k Gil lett, Glenn Herdeg, B i l l L i n , B i l l Schmidt, Jim S t a p l e s , B e r r y A n n Tyso n . B o b W i l l a r d . Of cou rse, the VA.XBI bus wou ld not have been pos­ sible withour the contributions of the VLSI team respo n s i b l e for t h e 7 8 7 3 2 VAX B I I n te rface Chip.

References

1 . F . Bomba . R. Chen, and R . G i l l ett, "Gen­ eral Purpose Bus Eases Interaction of Dis­ tributed Resources, " Computer Technol­ o gy R e v i e w , v o l . V I , n o . 2 ( S p r i n g 1 986) : 4 7 - 5 3 .

2 . VA XBJ Op tio n s Ha ndbook ( M aynard , D i g i t a l Equ i p m e n t Corporati o n , Order No. EB- 2 7 2 7 1 -4 6 , 1 986) .

3 . R . Sch u ma n n and W . Parker, " A 3 2 - b i t B u s In terface C h i p . " JSSCC Diges t of Technical Papers . vol . XXVII (February 1 984 ) : 1 4 7- 1 4 8 .

4 . SPICE was developed by Lawrence Nagel a n d E l l i s C o h e n of the Depa r t m e n t of E lectrical Engineering and Computer Sci­ ence , University of California, Berkeley.

Digital Technical journal

No. 4 February I '/87

New Products

Michael W. Kement

I

Gerald]. Brand

A Logical Grounding Scheme for