Capítulo 6
Desarrollo hardware.
VREFHI
0
2
D2
LN1861C D1
LN1861C
VCC
R9
33 C1
.
R2
330 3
0
0
R5
330 R6
330
D8
LN1861C R7
330 R4
330 R3
330
D5
LN1861C
L1 .
0 U12
TMS320C240
84 85 86
87 8 59
72 73 74 75 76 78
80
63 64 65 66 67 68 69 70
100 101 102 105 106 107 108 109
57 58
53 54 55 52 40
9
129 131 130 4 6 1 132 5
94 95 96 97 98 79
91 90 89 88 83 82 81 77
36 35 37 41 42 56
2 13 21 47 62 93 103 121 7 60 50
10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
99
32 33 31 34 30 38 39
120
3 14 20 29 46 61 71 92 104 113
VCCA VREFHI VREFLO
VSSA VSS VSS
ADCIN0/IOPA0 ADCIN1/IOPA1 ADCIN2 ADCIN3 ADCIN4 ADCIN6
ADCIN15
ADCSOC/IOPC0 CLKOUT/IOPC0 XF/IOPC2 BIO/IOPC3 CAP1/QEP1/IOPC4 CAP2/QEP2/IOPC5 CAP3/IOPC6 CAP4/IOPC7
PWM7/CMP7/IOPB0 PWM8/CMP8/IOPB1 PWM9CMP9/IOPB2 T1PWM/T1CMP/IOPB3 T2PWM/T2CMP/IOPB5 T3PWM/T3CMP/IOPB5 TMRDIR/IOPB6 TMRCLK/IPB7
XTAL2 XTAL1/CLKIN
XINT1 XINT2/IO XINT3/IO PDINT NMI
D0
DS PS IS R/W STRB WE W/R BR
PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 ADCIN7
ADCIN8/IOPA3 ADCIN9/IOPA2 ADCIN10 ADCIN11 ADCIN12 ADCIN13 ADCIN14 ADCIN5
READY RS MP/MC PORESET PMTMODE OCBYP
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VCCP
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
PWM6/CMP6
TRST TMS TDI TD0 TCK EMU0 EMU1/OFF
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VCCA
JP2
R8
330 R1
330
D4
LN1861C 2
Conexión de un array de 8 LEDs al TMS320C240 Title
VDD
JP1
0 VCC VREFLO
0
U1
10Mhz VCC
GND OUT 3
CLKIN
D7
LN1861C 0
1
0
D6
LN1861C
1
D3
LN1861C
0
VCC
SW1
SW DIP-8/SM 0
VDD
JP1
VCC
0
CLKIN
3
Esquema 2
Conexión de 8 interruptores tipo DIP para la entrada del TMS320C240
A3
1 1
Thursday, March 01, 2007 Title
Size Document Number Rev
Date: Sheet of
R7 10K R3
10K U12
TMS320C240
84 85 86
87 8 59
72 73 74 75 76 78
80
63 64 65 66 67 68 69 70
100 101 102 105 106 107 108 109
57 58
53 54 55 52 40
9
129 131 130 4 6 1 132 5
94 95 96 97 98 79
91 90 89 88 83 82 81 77
36 35 37 41 42 56
2 13 21 47 62 93 103 121 7 60 50
10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
99
32 33 31 34 30 38 39
120
3 14 20 29 46 61 71 92 104 113
VCCA VREFHI VREFLO
VSSA VSS VSS
ADCIN0/IOPA0 ADCIN1/IOPA1 ADCIN2 ADCIN3 ADCIN4 ADCIN6
ADCIN15
ADCSOC/IOPC0 CLKOUT/IOPC0 XF/IOPC2 BIO/IOPC3 CAP1/QEP1/IOPC4 CAP2/QEP2/IOPC5 CAP3/IOPC6 CAP4/IOPC7
PWM7/CMP7/IOPB0 PWM8/CMP8/IOPB1 PWM9CMP9/IOPB2 T1PWM/T1CMP/IOPB3 T2PWM/T2CMP/IOPB5 T3PWM/T3CMP/IOPB5 TMRDIR/IOPB6 TMRCLK/IPB7
XTAL2 XTAL1/CLKIN
XINT1 XINT2/IO XINT3/IO PDINT NMI
D0
DS PS IS R/W STRB WE W/R BR
PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 ADCIN7
ADCIN8/IOPA3 ADCIN9/IOPA2 ADCIN10 ADCIN11 ADCIN12 ADCIN13 ADCIN14 ADCIN5
READY RS MP/MC PORESET PMTMODE OCBYP
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VCCP
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
PWM6/CMP6
TRST TMS TDI TD0 TCK EMU0 EMU1/OFF
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VREFLO
3
R4 10K
L1 .
VREFHI
0
C1 .
U1
10Mhz VCC GND
OUT
JP2
0
R9 10K R5
10K
R1
33
1
1
R2 10K
R6 10K VCCA
2
0
R8 10K VCC
0
0
2
R5 1K 1
0
3 SCITXD/IO
VCCA
0
0 C2 CAP NP
2
JP2
0 C3 CAP NP
2
1 JP3
0
2 VREFLO
VREFHI
R3
1K
CLKIN P1
CONNECTOR DB9 5 9 4 8 3 7 2 6 1
0
0
1
L1 .
Esquema 3
Conexión de un puerto serie DB9 al TMS320C240
A3 Title
Size Document Number Rev
JP4 3
VCC
VCC
3
JP1 C5
CAP NP
2
JP5
U13
10Mhz VCC GND
OUT 0
HOSTRESET
0 R4 1K
Q1
MAX232A 1
3
2
4 5 11 10 13
8 12
9 14 7 6 C1+
C1- V+
C2+
C2- T1IN T2IN R1IN R2IN
R1OUT R2OUT T1OUT T2OUT V-
0
R1
33 C1
. 1
3
U12
TMS320C240
84 85 86
87 8 59
72 73 74 75 76 78
80
63 64 65 66 67 68 69 70
100 101 102 105 106 107 108 109
57 58
53 54 55 52 40
9
129 131 130 4 6 1 132 5
94 95 96 97 98 79
91 90 89 88 83 82 81 77
36 35 37 41 42 56
2 13 21 47 62 93 103 121 7 60 50
10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
99
32 33 31 34 30 38 39
120
3 14 20 29 46 61 71 92 104 113
VCCA VREFHI VREFLO
VSSA VSS VSS
ADCIN0/IOPA0 ADCIN1/IOPA1 ADCIN2 ADCIN3 ADCIN4 ADCIN6
ADCIN15
ADCSOC/IOPC0 CLKOUT/IOPC0 XF/IOPC2 BIO/IOPC3 CAP1/QEP1/IOPC4 CAP2/QEP2/IOPC5 CAP3/IOPC6 CAP4/IOPC7
PWM7/CMP7/IOPB0 PWM8/CMP8/IOPB1 PWM9CMP9/IOPB2 T1PWM/T1CMP/IOPB3 T2PWM/T2CMP/IOPB5 T3PWM/T3CMP/IOPB5 TMRDIR/IOPB6 TMRCLK/IPB7
XTAL2 XTAL1/CLKIN
XINT1 XINT2/IO XINT3/IO PDINT NMI
D0
DS PS IS R/W STRB WE W/R BR
PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 ADCIN7
ADCIN8/IOPA3 ADCIN9/IOPA2 ADCIN10 ADCIN11 ADCIN12 ADCIN13 ADCIN14 ADCIN5
READY RS MP/MC PORESET PMTMODE OCBYP
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VCCP
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
PWM6/CMP6
TRST TMS TDI TD0 TCK EMU0 EMU1/OFF
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0
SCITXD/IO
3
2
VCC
C4 CAP NP R2
4.7K
1
VDD
VCC
0 DACOUT4
U12
TMS320C240
84 85 86
87 8 59
72 73 74 75 76 78
80
63 64 65 66 67 68 69 70
100 101 102 105 106 107 108 109
57 58
53 54 55 52 40
9
129 131 130 4 6 1 132 5
94 95 96 97 98 79
91 90 89 88 83 82 81 77
36 35 37 41 42 56
2 13 21 47 62 93 103 121 7 60 50
10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
99
32 33 31 34 30 38 39
120
3 14 20 29 46 61 71 92 104 113
VCCA VREFHI VREFLO
VSSA VSS VSS
ADCIN0/IOPA0 ADCIN1/IOPA1 ADCIN2 ADCIN3 ADCIN4 ADCIN6
ADCIN15
ADCSOC/IOPC0 CLKOUT/IOPC0 XF/IOPC2 BIO/IOPC3 CAP1/QEP1/IOPC4 CAP2/QEP2/IOPC5 CAP3/IOPC6 CAP4/IOPC7
PWM7/CMP7/IOPB0 PWM8/CMP8/IOPB1 PWM9CMP9/IOPB2 T1PWM/T1CMP/IOPB3 T2PWM/T2CMP/IOPB5 T3PWM/T3CMP/IOPB5 TMRDIR/IOPB6 TMRCLK/IPB7
XTAL2 XTAL1/CLKIN
XINT1 XINT2/IO XINT3/IO PDINT NMI
D0
DS PS IS R/W STRB WE W/R BR
PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 ADCIN7
ADCIN8/IOPA3 ADCIN9/IOPA2 ADCIN10 ADCIN11 ADCIN12 ADCIN13 ADCIN14 ADCIN5
READY RS MP/MC PORESET PMTMODE OCBYP
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VCCP
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
PWM6/CMP6
TRST TMS TDI TD0 TCK EMU0 EMU1/OFF
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
0 VREFHI
2
VCCA
VDD
CLKIN DACOUT2
VCCA
0
0 U13
10Mhz VCC GND OUT
VREFLO 1
ADCSOC/IOPC0
Esquema 4
Conexión de Puerto de entradas analógicas al TMS320C240
A3
1 1
Thursday, March 01, 2007 Title
Size Document Number Rev
Date: Sheet of
0
VCC
C1 .
0
2
J1
CON34A
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 19 21 23
25 26
27 28
29 30
31 32
33 34
18 20 22 24 DACOUT1
JP1 VCCA
VREFLO
L1 .
3
0
0
3 JP2
0 DACOUT3
R1
33
VREFHI
1
C1 . 0
SCIRXD/IO
VDD
0
JP2
CLKIN
0 VCC
PDPINT
0
VREFLO 1
0 J1
CON34A
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 19 21 23
25 26
27 28
29 30
31 32
33 34
18 20 22 24
Conexión de puerto de I/O digitales al TMS320C240 Title
R1
33 SPICLK/IO
JP1
1 VCC
SPISOMI/IO
2
0 L1
.
0
2
SCITXD/IO
SPISTE/IO VCC
U12
TMS320C240
84 85 86
87 8 59
72 73 74 75 76 78
80
63 64 65 66 67 68 69 70
100 101 102 105 106 107 108 109
57 58
53 54 55 52 40
9
129 131 130 4 6 1 132 5
94 95 96 97 98 79
91 90 89 88 83 82 81 77
36 35 37 41 42 56
2 13 21 47 62 93 103 121 7 60 50
10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
99
32 33 31 34 30 38 39
120
3 14 20 29 46 61 71 92 104 113
VCCA VREFHI VREFLO
VSSA VSS VSS
ADCIN0/IOPA0 ADCIN1/IOPA1 ADCIN2 ADCIN3 ADCIN4 ADCIN6
ADCIN15
ADCSOC/IOPC0 CLKOUT/IOPC0 XF/IOPC2 BIO/IOPC3 CAP1/QEP1/IOPC4 CAP2/QEP2/IOPC5 CAP3/IOPC6 CAP4/IOPC7
PWM7/CMP7/IOPB0 PWM8/CMP8/IOPB1 PWM9CMP9/IOPB2 T1PWM/T1CMP/IOPB3 T2PWM/T2CMP/IOPB5 T3PWM/T3CMP/IOPB5 TMRDIR/IOPB6 TMRCLK/IPB7
XTAL2 XTAL1/CLKIN
XINT1 XINT2/IO XINT3/IO PDINT NMI
D0
DS PS IS R/W STRB WE W/R BR
PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 ADCIN7
ADCIN8/IOPA3 ADCIN9/IOPA2 ADCIN10 ADCIN11 ADCIN12 ADCIN13 ADCIN14 ADCIN5
READY RS MP/MC PORESET PMTMODE OCBYP
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VCCP
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
PWM6/CMP6
TRST TMS TDI TD0 TCK EMU0 EMU1/OFF
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
0 3
0 SPISIMO/IO
VCCA
U13
10Mhz VCC GND
OUT 3
VCC VREFHI
