1 EXPRESIÓN DE CITOQUINAS EN EL CEREBRO DE RATAS VIEJAS: EFECTO DEL TRATAMIENTO CON GH O GHRP-

DSB/SSB ASK Switch Quadrature Up Mixer Quadrature LO PA Add BPF Coupling Direct TX Coupling Quadrature

Down Mixer LNA

Antenna

Wireless Channel

Free Space AWGN

Channel Free Space AWGN Channel BPF _Add Antenna LPF

AC Coupling Gain Saturation

Tag Reflection Tag Antenna Mixer Tag Antenna Tag Encode Scope Reader Receiver (RX)

Figure 2-10: The simulation environment of return link (Reader, Wireless channel and Tag) [37]

A simulation environment of complete return link of RFID reader, including the wireless channel and the tag, is illustrated in Figure 2-10. The transmitter sends a continuous carrier to power up the tag. The free space pass-loss is modelled for the distance between reader, tag and the noise source models in an AWGN channel. Another source of receiving power is the direct coupling from TX to RX. It is modelled by a proper gain and phase delay. The tag is modelled by coding method, antenna gain and percent of reflection by using the backscatter method. The receiver arm includes BPF, LNA, Mixer, AC coupling, channel select filter and the variable gain stage. The working procedures of the receiver are opposite to the transmitter. The completed simulation results can be presented by using different modulation and encoding types in transmitter from Jin and Cheng’s paper[37].

In terms of practical implementation, a single-chip reader is feasible for UHF RFID since the higher operating frequency results in a smaller size of antennas and passive components. Among various solutions, the standard CMOS technology and the direct- conversion architecture are popular methods represented in reduced cost, low power consumption, and improved the level of integration. In passive UHF RFID system the

design is much more challenging. Tags are expected to be as “simple” as possible and its operating power is limited. These requirements will lead to increase in design complexity and performance of the receiver.

In passive UHF RFID system, the tags are powered from the reader. If the tag is the corresponding one, the communication link between the reader and the tag will be established. Then the reader sends the DSB/SSB/PR-ASK modulated signal to command the tag and subsequently transmits the continuous-wave (CW) signal to ensure the tag remains energised.

RFID Tag

þ0ÿ þ1ÿ

Backscattered from RFID Tag CW Signal (Modulated DSB/SSB/PR-ASK) LNA Leakage _V LO-I VLO-Q Rx Baseband Tx PA Tx Baseband VLO-I VLO-Q Rx,OUT-I Rx,OUT-Q Tx,OUT-I Tx,OUT-Q Tx Front-end Rx Front-end Down Mixer Up Mixer Reader Transceiver

Figure 2-11: The front-end block of a typical RFID Reader[12]

However, limited isolation between transmitter (Tx) and receiver (Rx) can cause a leaking problem. Leaked signal from a transmitter can saturate the receiver, hence inducing severe noise performance degradation or even blocking the expected signal from the tags. In general, this DC leakage signal (self-jammer) from transmitter is much larger (over 10dBm) than the wanted signal from tags (down to -80dBm) [38]. Therefore, the RF front-end of the reader needs to have extremely high linearity to handle the carrier leakage problem and the trade-off between linearity and noise figure becomes the greatest challenge for RFID reader receiver.

Several methods have been proposed to remove the DC leakage [39-42]. A self-jammer cancellation circuit with off-chip capacitors is employed in [39] to remove the DC leakage. It achieves sufficient linearity and good sensitivity in the presence of large leakages. However, it is based on the SiGe BiCMOS and requires a 5 V supply voltage. The use of off-chip capacitors to handle the DC leakage results in large power consumption up to 1.5 W. However, the fully differential I/Q receiver structure requires four off-chip capacitors and eight pins in the package.

Another scheme, reported in [40], used a front-end structure that consists of a passive mixer without LNA to achieve high linearity. However, the NF and receiver sensitivity, as functions of time, deteriorated significantly. In contrast, a LNA was partially employed in [43] to prevent the demodulator from saturation during listen-before-talk (LBT) mode, with a trade-off of degrading the receiver sensitivity and the dynamic range of the receiver. In [44, 45], on-chip intelligent canceller (carrier suppression) is used to counteract the leakage carrier from Tx to Rx but at the cost of larger size and additional calibration control[42].

Recently, on-chip DC offset correction circuits (DCOC) have gained popularity due to their linearity and sensitivity without removing the LNA[38, 43]. This kind of architecture consists of an LNA, a passive down-conversion mixer, a baseband programmable gain amplifier (PGA) and a few low pass filters (LPF). Direct conversion (Zero-IF) architecture is selected to overcome the carrier leakage problem. Since the LO frequency equals to RF input carrier frequency, the received signals are mixed down to the baseband and the carrier leakage components is converted to DC that can be removed by AC-coupling. The passive mixers are commonly chosen to offer higher linearity to avoid the in-band blocker from carrier leakage. In the baseband, quadrature I/Q paths cooperate with four PGA to provide a wide gain control range. The baseband low pass filter is an active-RC filter with a programmable 3-dB bandwidth from 100 kHz to 1.6 MHz depending on the different Rx data rate. However, the settling time of the on-chip DCOC circuit might become longer when the DC leakage is larger. In [38], an on-chip SC circuit was proposed with quickly time-varying cut-off frequency and on-chip DCOC circuit to kill the DC leakage. However, like any other direct-conversion receivers, the baseband analogue modules are still susceptible to the DC offset, especially in CMOS technology.

In addition, the I/Q direct-conversion Rx structure is preferred to eliminate the zero- effect in terms of UHF RFID applications for different phase delay from variable operation distance [46]. The limited LO phase noise performance would significantly exacerbate Rx input noise floor and the transmit-to-receiver turnaround time.

Therefore, in this thesis, an active highly linear RF front-end is designed to provide good trade-offs between power consumption, linearity, noise and sensitivity for achieving optimal performance.