2 EXPRESIÓN DE CITOQUINAS Y QUIMIOQUINAS EN LA HIPÓFISIS DE RATAS VIEJAS: EFECTO DEL TRATAMIENTO CON GH O GHRP-

In the transceiver design, the local oscillator (LO) provides carrier signals for signal conversion in front-end. As mentioned earlier, this process of frequency conversion is also called heterodyning. Oscillators are usually embedded as part of the phase-locked system. A voltage-controlled oscillator (VCO) has gained its dominance in oscillator design due to its flexible frequency tuning ability. In terms of waveform generation trends, oscillators can be classified as either the harmonic oscillator or the relaxation oscillator[112].

Ideal harmonic oscillators produce linear periodic sinusoidal output. A typical form of a harmonic oscillator is a feedback loop consisting of an amplifier and filter. The inherent noise is filtered and re-amplified until it resembles the desired signal. As such a circuit has no input while sustaining the output indefinitely, and a negative resistance or positive feedback system is used to form an oscillator. Almost all the well-known oscillators, such as the Colpitts oscillator[113], Hartley oscillator[114], Clap oscillator [115] and so on, are used in the feedback system with a LC harmonic resonate circuit. In contrast, a relaxation oscillator produces a non-sinusoidal output and contains nonlinear components. The active components (transistors) periodically discharge the energy stored in a capacitor or inductor to cause the disturbed changes of the output waveform. Ring oscillators are an extremely popular member, since they are derived from digital-like building blocks. Even they occasionally have inferior phase noise for a given level of power consumption compared to harmonic tuned oscillators; their relatively large tuning range and simplicity are attractive enough for many applications. However, relaxation oscillators are rarely used in high-performance transceivers because they generate signals of inadequate spectral purity[31].

The simplest LC circuit resembles a resonant “mass-spring” system. The active device joins the system to overcome the harmonic damping effect. Most of the tuned harmonic oscillators are named by those who first develop the topologies, but as seen in Figure 2- 24, these designs appear more or less similar to the unified description. In the Colpitts oscillator, a capacitive voltage divider off the tank provides feedback to the amplifier. A sketch of the root locus shows the feedback is positive with a band pass filter. Rather than a tapped capacitor, a tapped inductor for feedback is implemented in the Hartley oscillator. The Clapp oscillator is a modified version of Colpitts’ oscillator, with a series LC replacing the single inductor. It offers an additional tap on the capacitive diver chain that allows an excessive voltage swing across the inductor. Among these topologies, the Colpitts is certainly the most commonly used topology due to its excellent phase noise performance. Crystal oscillators are later derived from the above LC structure to provide more stable and accurate tuning frequency.

C1 C2 L R L1 L2 C R C1 C2 L R (a) (b) (c)

Figure 2-24: (a) Colpitts oscillator (b) Hartley oscillator and (c) Clapp oscillator

In the last decade, the differential cross-coupled LC oscillators have gained in popularity as they produce a more practical negative resistance, as shown in Figure 2-25 (a)[116-118]. The symmetrically half-circuit implied a negative resistor that is essentially identical from above equivalent circuits. A variable MOS capacitor is commonly used nowadays for extra tuning capability of the oscillator, as shown in Figure 2-25 (b) [119]. The current reusing complementary cross-coupled topology used in Figure 2-26 was proposed afterwards to overcome the voltage swing limit issue [120, 121], but with higher power consumption.

L L C Ibias L L _V ctrl Ibias (a) (b)

Figure 2-25: (a) Simple differential negative resistance oscillator and (b) Voltage- controlled negative resistance oscillator.

Vctrl

I

tail

Itail

Itail

Figure 2-26: Current reusing complementary VCO topology

As discussed earlier, quadrature output is required for images rejection application. An oscillator architecture that naturally provides quadrature output uses a pair of integrators in a feedback loop. The Original (QVCO) was based on the cross-coupling of two differential LC VCOs [121-123]. This structure has coupling transistors and switch transistor in parallel that has poor phase-noise behaviour, as shown in Figure 2-27 (a). In order to improve the phase noise, the cross-coupling transistors were later placed in series with switch transistor rather than in parallel [29, 124, 125]. The structure with the

coupling transistor on the top of the switch transistor is known as a top-series QVCO (TS-QVCO), as shown in Figure 2-27 (b). Alternatively, a bottom-series QVCO (BS- QVCO) has the coupling transistor at the bottom as illustrated in Figure 2-27 (c). Simulations show that the BS-QVCO has better phase noise and higher phase error than the parallel QVCO and TS-QVCO[126].

Ibias (a) Ibias I+ I+ I- I- Q+ Q+ Q- Q- Ibias (b) I+ I- Q+ Q- Ibias I+ I- Q+ Q- Ibias I+ I- Q+ Q- (c) Ibias I+ I- Q+ Q-

Figure 2-27: Schematic of (a) parallel QVCO (b) top-series QVCO[124] (c) bottom- series QVCO[126].

Since the telescopic cascode structure along with the tail current source constrains the voltage headroom, these topologies are not very suitable for today’s deeply scaled power supplies, especially with symmetrical structures [127, 128]. They consume more power due to the stacking of the symmetrical coupling transistors in series with the switch transistors that generate negative resistance. Even low-voltage operation involving transformer coupling has been investigated [129]; it generally requires a large bias current through a single tail device, resulting in severe bandwidth versus headroom trade-off. The current reusing technique along with back-gate coupling uses less power but requires two extra bias voltages for optimal back-gate biasing[130]. VCO design with folded-cascode topology was introduced in 2010 with the advantages of requiring low power supplies and low power dissipation[131]. This topology will be investigated in the following chapter, where detailed analysis and simulation results will be presented and the topology’s advantages and disadvantages will be discussed. In the meanwhile, the definition of phase noise and its numerical expression is reviewed for selection of better solution in an RFID receiver front-end.