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As the octal transcei ver test c h i p was being deve l ­ oped , M S D , JRDC a n d SEG conducted architec­ ture and performance studies . These studies wou ld a nswer questions about the organization of t he SjG mapping function, the data buffering req u i red to meet t he performance goals, and the seq uential control l ers part i t ioni ng and clocking to manage the two asynchronous buses and t he i n ternal function s .

SjG Mapping

A RAM structure was first proposed to implement t he SjG mapping functional ity. The MicroVAX I I CPU design had used such a structure, with two 8K-by-8 static RAMs . This proposal , however, was rejected s i nce not a l l of t he RAM woul d tit on a si ngle chip with a l l the other requ i red circ u i try. I ncreasing t he c h i p size was not an option . The c h i p s i ze was l i m i ted for cost reasons as wel l as packaging cavity size reasons. The c h i p 's cost is d i rectly proportionate ro its size, and t he design of a new package was outside t he scope of t he project. Moreover, implementation of a portion of the RAM wou ld have i ntroduced a system soft­ ware i ncompati b i lity with MicroVAX I I and woul d have reduced t he p l a n ned performance .

As the probl e m of SjG mapping functional i ty was stu d ied, i t became clear that system memory was adequate. rurther, CQBlC cou ld not i m p le­ men t the fu l l 8 1 9 2 -entry RAM on a c h i p size that cou ld be fabricated with reasonable yield . Also, a capabi l i ty to prefetch S/G map entries based on expectation was considered necessary to susta i n peak, a s opposed to average, performance . We looked to t he Q 2 2 - bus DMA devices which per­ form transactions w i t h i ncrementing addresses. I n particu lar, Q 2 2 -bus devices are designed to u t i lize the Q 2 2 -bus block-mode data transfer protocol . This protocol transfers data packers of eight-word b locks . With this protocol avai lable, we could design t he CQBlC tO cache the SjG map e ntries from system memory on demand and on expectation .

The next two problems were how to i mple­ ment the cache and how many e ntries to i nc lude in the cache. A 1 6-entry cache provided t he bal ­ ance we sought between several factors: appro­ pri a te chip area, i m pl ementation complexity , design risk, a nd DMA 1 / 0 performance i m pact.

Development of the C VAX Q22- hus Interface Chip

Data Buffering

CVAX bus cyc le ti mes were targeted to be four or more ti mes greater than typical Q 2 2 -hus cycle t i mes. Abo. the CVAX bus was being designed ro support DMA mult idata transfers . This design was consistent with the Q 2 2 -bus block-mode data transfer prorocol . To bridge the bandwidth gap between the two buses and ro m i n i mize the use of CVAX bus bandwidth, data bufferi ng tech­ niq ues were i nvestigated to opt i mi ze for Q 2 2 -bus block-mode throughput for read and wri te t rans­ actions . These investigations resu.lted not on l y i n t h e determi nation of buffer s izes but also i n a decision on how to control the: buffers to opt i ­ m i ze sustai ned throughput and m i n i m i ze i n i t ial l atency .

The MicroVAX l l CPU is capable of supplying read data to the Q 2 2 -bus with a very consistent access t i me because memory arbi tration is nor requ i red . To achieve MicroVAX I I average read performance , read data prefetching was consid­ ered necessary to compensate for the memory arbitration time . For CQBIC. the first read of a Q 2 2-bus transaction would be t i me delayed by the DMA request and grant t i me , to obta i n master­ ship of the CVAX bus . a nd by rhe subsequent sys­ tem memory access r i me The de: lay wou ld a lways he longer than M icroVAX I I read l atency. which had on ly memory access t i me read latency ro consider. We determi ned that rwo q uadword read buffers wou ld be sufficient to sustain the n:q u i recl throughput because read data is prcfetched based on expectations of the Q 2 2 bus block-mode protocol . Low latency was achieved by provid i ng a response to the Q 2 2 - bus as the first longword of the quadword read data was obta i ned from system memory .

Pipe lin ing the buffered wri te data cou ld be ach ieved with two buffers. each eight words deep. An ocraword block is the packet size of the Q 2 2 -bus block-mode protocol and is rhe max i ­ m u m multi transfer block size o f the CVAX bus. The conrrol logic wou ld be designed to al l ow one buffer ro be unloaded ro system memory while t he other was being h l led . The latency wou ld be better than that of the M icro VAX I I CPU mod u l e , since the CQBIC data was packed i nto fast octa­ word buffers . The average throughput wou ld be sustained by t he four t i mes or greater bandwidth of the CVAX bus, as compared to the Q 2 2 -bus, by t he use of pipe l i ned data buffers.

The CQBIC buffering and transact ion opt i m i za­ tions in conju nct ion wirh the CVAX CPU internal

U 2

cache h i t rate result in an i nsigni ficant DMA ljO i m pact on CVAX CPU performance . G iven the buffering and control orga n i zation and opti m i za­ t ions described above , performance d i fference between the s i ngle-port and the dual-port mem­ ory designs cannot be detected by a Q 2 2 -bus device. The resu lt is i mprovement in Q 2 2 -bus read and write t hroughput over the M icroVAX I I CPU. The CQBIC maximizes Q 2 2 -bus perfor­ mance and m i n i m i zes CVA,'( bus usage . Moreover, CQBIC can sustai n Q 2 2 -bus block-mode transfer write data rates of 3 .1 megabytes (MB) per sec­ ond and read data rates of 2 . 5 MB per second

Fi n a l l y , ro opt i m i ze t he CVAX ljO write perfor­ mance . a du mp-and - run buffer was ro be i mple­ mented in CQBIC This buffer is used ro avoid tying up the CVAX bus while the slower Q 2 2 -bus transaction completes and whi l e dead lock situa­ t ions are resolved.

Controller Partition

G iven these buffering functions, the control of the data pat h and of the two major bus interfaces was natu rall y part i tioned into five l inked con­ trol l ers and a prioritization fu nct ion . Each bus interface was partitioned i n to a master and a slave control ler. The S/G map cache also req u i red a control l e r . Then ro assist i n coord ination of con­ t rol tlow decisions, a priority resolver function was needed .

This part i tion al lows the Q 2 2 -bus and the CVAX bus to operat e i n paral lel while all dead­ lock condi t ions arc resolved . Fortunate ly the CVAX chi p team i mp le mented a bus transaction ret ry capabi l i ty . This retry capabi l i ty proved essenti a l to our part i t ion and i mplementation of CQBIC control functional i ty .

Clocking

Two primary factors led us to select a 5 0-nano­ second ( n s ) two-p hase nonoverlapped i nternal clock scheme . First, the MicroVAX I I CPU mod­ u l e 's '5 0-ns single-phase clocki ng sc heme was a proven approach and mapped we l l to the fi xed Q 2 2 -bus m i ni mum asynchronous t i m i ng speci fi ­ cations. Second , w e ex pected synchronous CVAX bus cyc l e t i mi ng to vary with CMOS technology i m provements. The variable CVAX cycle t i me and four-phase overlapped clock i n g scheme cou ld not be used to generate the fixed Q 2 2 - bus t i m ­ ing. Also . havi ng two clocking sc hemes i n one c h i p was determ ined tO be a design too com plex ro manage .

Digital Technical journal

The impl icat ion of the sc lccrccJ CQBIC clock­ ing scheme was that. with reference tO a l l inter­ nal cont rol l ers. the CVAX bus and the Q 2 2-bus were asynchronous.

Research Results Sum mary

The resu l t of the research was a si ngle c h i p design that wou l d achieve t h e stated project goa ls by provid ing

• Integra l Q 2 2-bus transce ivers

• A 1 6-cntry map cac he . with preferc h i ng • Two octaword Q 2 2 -bus write buffers

• Two quadword Q 2 2-bus read buffers . with

prefetching

• A longword CVAX write buffer

• Transaction part i tioned sequent ial control l ers .

which are opt i m ized for Look-ahead data bulfcring cont rol and for u t i l ization of m u l t i ­ ple-transfer transactions t o m i n i mi ze CVA.X bus and Q 2 2-bus usage

The research n.:su lts were docu mented in the form of a revised c h i p spec i fication and a be hav­ ioral mode l . The c h i p was i m pl emented from the revised specification with a process which was

unique and unproven