A propósito de la Interoceánica

is chapter has outlined the development of a high performance soware radar processor. Each factor which limited performance was identified and carefully optimised.

ble threaded design was adopted whereby computation tasks were divided across a number of separate threads. As a consequence, the radar soware remains responsive to user input and is capable of receiving new data quickly without dropping frames. e division of each frame among a number of worker threads allows the soware to make full use of the computational resources available to it.

Hardware accelerated rendering was implemented using the industry stan- dard OpenGL application programming interface. By allocating this work to the graphics processor, demand for CPU resources was reduced, thereby increas- ing the overall system performance. A workaround was implemented to allow OpenGL to be integrated with the LabWindows/CVI environment.

An innovative lookup-table method was developed to enable efficient loga- rithmic colour-scaling. is algorithm employs low-level bit manipulation of the internal structure of a floating point variable in order to bypass the need to di- rectly compute the logarithm. In benchmarks, this algorithm performed almost 22 times faster than a conventional colour-scaling routine.

A GPU-based colour scaling method was developed which was implemented using a programmable OpenGL fragment shader routine. is routine further reduces the CPU workload, thereby increasing performance. Where support for programmable fragment shaders isn’t available, the CPU-based routine is avail- able as an alternative.

In benchmarks, the Microso Visual C compiler completed radar processing 430% faster than the LabWindows/CVI non-optimising compiler. For this rea- son, the Microso Visual C compiler was adopted. e FFTW fast Fourier trans- form library was benchmarked against the FFT routines provided within LabWin- dows/CVI, revealing a 50% performance increase over its fastest routine.

is soware radar processor was wrien to be as abstract and modular as possible. is flexibility allowed it to be easily adapted to two surveillance radars, NIRAD and IRAD. is work is outlined in chapter 3. Additionally, the techniques which have been outlined in this chapter were applied to enhance the perfor- mance of the radar control soware of two radar systems, SAFIRE and AVTIS. is work will be discussed in chapters 5 and 6.

Chapter 3

NIRAD and IRAD

3.1 Introduction

NIRAD [21] and IRAD [17, 52] are two millimetre-wave security radars which were developed within the Millimetre-wave Group in St Andrews, by Dr Duncan Robertson. NIRAD (Non-Imaging RADar) is a perimeter surveillance radar which operates at 94 GHz. IRAD (Imaging RADar), is a volumetric imaging radar which operates at 340 GHz. While IRAD was designed for operation at larger stand- off distances, its focus has been adjusted for operation at a stand-off distance of 20 m. IRAD’s beam is steered in azimuth and elevation by a pair of scanning mirrors. ese radars were originally envisioned as complementary, with NIRAD counterbalancing IRAD’s restricted field of view. Table 3.1 compares the typical operating parameters of NIRAD and IRAD.

NIRAD IRAD Units

Frequency 94 340 GHz

Bandwidth 600 3600 MHz

Range resolution 25 4.2 cm

Chirp duration 102.4 102.4 µs

Sampling rate 10 10 MSa/s

Time samples 1024 1024

Lines of sight per frame 1024 1296

Frame rate 8.8 6 Hz

Transmit power 100 0.25 mW

Data rate 591 510 Mbps

Table 3.1: Comparison of typical operating parameters of NIRAD and IRAD.

NIRAD and IRAD share a common RF architecture, both employing a hetero- dyne down-conversion scheme. All signal sources are referenced to a fixed 10 MHz master oscillator, allowing phase coherency to be preserved chirp-to-chirp. e linear frequency chirp is generated using a direct digital synthesiser (DDS), and is up-converted to 7.83 GHz prior to frequency multiplication. Direct digital synthesis is performed using an AD9910 evaluation board driven by an external 1 GHz reference clock. e frequency ramp is generated using the AD9910’s in- ternal digital ramp generator. Radar baseband output is carried by coaxial cable from the radar to a standard desktop computer with an Acquitek CH-3160 four channel ADC expansion card installed, where it is sampled and processed in so- ware. e ADC is operated in a burst acquisition whereby a fixed number of samples are collected in response to an external trigger. e acquisition time of the ADC and ramp duration of the DDS are matched and triggered simultane- ously. e trigger signal is either derived from a fixed frequency oscillator in the case of a staring measurement, or derived from the scanner position when the radar is operated in scanning mode.

e soware radar processor, which is outlined in chapter 2, was adapted to control both NIRAD and IRAD, resulting in significant enhancements to their performance, allowing them to operate at the performance limit of their hard- ware. Furthermore, several hardware enhancements were made to enable coher- ent measurement. is includes the incorporation of an 80 MHz ADC reference clock derived from the 10 MHz master oscillator and new timing circuitry based on an Atmel ATMEGA328 8-bit microcontroller.