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[PDF] Top 20 Improving Transactional Memory Performance for Irregular Applications

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Improving Transactional Memory Performance for Irregular Applications

Improving Transactional Memory Performance for Irregular Applications

... In general, extracting thread parallelism from a sequential program requires decomposing the program into tasks and the correct computation of dependencies between these tasks. Com- puting such dependencies statically ... See full document

11

Improvements in Hardware Transactional Memory for GPU Architectures

Improvements in Hardware Transactional Memory for GPU Architectures

... implementation). Applications with read-only transac- tions such as HT and GC benefit from the shared signatures provided by sWO- sig, as this mechanism is able to filter out false read-read ...conflicts. ... See full document

17

TítuloPerformance analysis of HPC applications in the cloud

TítuloPerformance analysis of HPC applications in the cloud

... available for both types of guests, the domU guest “sees” a real device and interacts with it directly, without software intermediaries, improving the performance since no dom0 involvement is ... See full document

27

Transactional memory on heterogeneous architectures

Transactional memory on heterogeneous architectures

... and applications: from cell phones to supercomputers, going through cars and smart ...capabilities. For instance, OpenCL [38] provides an interface to program and communicate different devices maintaining ... See full document

158

Improving redundant multithreading performance for soft error detection in HPC applications

Improving redundant multithreading performance for soft error detection in HPC applications

... point; for that, the authors decide to kill the main process and fork a new ...volatile memory accesses, because given the scheme the leading process is allowed to execute unsafe operations without a check ... See full document

76

ReduxSTM: Optimizing STM designs for Irregular Applications

ReduxSTM: Optimizing STM designs for Irregular Applications

... a transactional system can be considered unordered, as the first transaction that comes to commit, with validated datasets, ...substitute for critical sections. When used as a tool for parallelizing ... See full document

22

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

... battery for their ...market for these types of devices grows, industry focuses on designing energy-efficient low- power ...designed for performance and a set of LITTLE cores designed ... See full document

5

Architectural support for high-performing hardware transactional memory systems

Architectural support for high-performing hardware transactional memory systems

... coarse-grain applications spent more time in the eager mode, given that large transactions that overflow the L1 cache do not support the lazy execution mode and conservative conflict management reduce drastically ... See full document

208

Enhancing the efficiency and practicality of software transactional memory on massively multithreaded systems

Enhancing the efficiency and practicality of software transactional memory on massively multithreaded systems

... seven applications from the Recognition, Mining and Synthesis (RMS) domain that are considered representative of future workloads for multi-core ...adequate for early experiments with ... See full document

227

Profiling and Analysis of Irregular Memory Accesses of Memory-Intensive Embedded Programs-Edición Única

Profiling and Analysis of Irregular Memory Accesses of Memory-Intensive Embedded Programs-Edición Única

... between memory and processor performance results in the mem- ory subsystem becoming the primary system-level bottleneck, particularly for memory- intensive embedded system applications ... See full document

258

Communion: a new strategy for memory management in high-performance computer systems

Communion: a new strategy for memory management in high-performance computer systems

... event-driven memory hierarchy simulators for ...compiled for a MIPS R3000 based ...code for simulation or to ...a memory reference generator (the “front- end”), and a target system ... See full document

18

 High performance thin film organic lasers for sensing applications 

 High performance thin film organic lasers for sensing applications 

... Furthermore, we have explored the sensing applicability of DFBs [7, 8, 9]. The feasibility of organic DFB laser sensors consisting of active films of PS doped with the PDI-O laser dye as bulk refractive index sensors has ... See full document

9

Analysis of individual flows performance for delay sensitive applications

Analysis of individual flows performance for delay sensitive applications

... Despite of the chosen approach we can identify difficulties when considering SLA assurance for delay sensitive applications. First, in the case of admission control mechanisms, we didn’t find any ... See full document

15

Energy improvements of CO2 transcritical refrigeration cycles using dedicated mechanical subcooling

Energy improvements of CO2 transcritical refrigeration cycles using dedicated mechanical subcooling

... try to reach the performance of other solutions. Aprea & Maiorino (2008), Torrella et al. (2011) and Sánchez et al. (2014) studied the improvements due to the use of internal heat exchangers (IHX) in single- ... See full document

28

Performance Evaluation of Applications for Heterogeneous Systems by means of Performance Probes

Performance Evaluation of Applications for Heterogeneous Systems by means of Performance Probes

... useful for any scheduling logic that needs information about how a given computing ele- ment will perform while running an application can benefit from the use of ...the performance prediction given by our ... See full document

2

FPGA-Based Wireless Sensor Node Architecture for High Performance Applications

FPGA-Based Wireless Sensor Node Architecture for High Performance Applications

... The capability of carrying out hardware reconfiguration, partially and at run time, opens a wide variety of new opportunities for WSNs. The possibility of loading different hardware modules depending on the ... See full document

124

Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems

Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems

... ever, the hardware irrevocability mechanism does not discard the transactional work done so far. The other transactions are stalled when a transaction gets irrevocable. Furthermore, the irrevocable one does not ... See full document

13

CALL FOR APPLICATIONS TO THE MEMORY OF THE WORLD REGISTER FOR LATIN AMERICA AND THE CARIBBEAN 2015

CALL FOR APPLICATIONS TO THE MEMORY OF THE WORLD REGISTER FOR LATIN AMERICA AND THE CARIBBEAN 2015

... process for candidacies of documents or sets of documents – from archives or libraries, text (handwritten or printed), audiovisual (film, video, sound recording), iconographic (photography, engraving, design) or ... See full document

8

SIAMPP14Slides.pptx

SIAMPP14Slides.pptx

... formulation of the Krylov method BICGSTAB ( CA-BICGSTAB ) as a high-performance, distributed-memory bottom solve routine for geometric multigrid solvers.. – Synthetic benchmark (min[r] ... See full document

32

Methods for Improving Escalators

Methods for Improving Escalators

... Linear Velocity (m/s) of Rollers Moved by One Roller Following a New Guide Shape using Two Links per Step (above), Minimum Distance (mm.) Between.. Driving and First Rollers (below).[r] ... See full document

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